1# Copyright 2018 Google, Inc. 2# 3# Redistribution and use in source and binary forms, with or without 4# modification, are permitted provided that the following conditions are 5# met: redistributions of source code must retain the above copyright 6# notice, this list of conditions and the following disclaimer; 7# redistributions in binary form must reproduce the above copyright 8# notice, this list of conditions and the following disclaimer in the --- 11 unchanged lines hidden (view full) --- 20# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25# 26# Authors: Gabe Black 27 |
28from m5.SimObject import SimObject, cxxMethod |
29 30# This class represents the systemc kernel. There should be exactly one in the 31# simulation. It receives gem5 SimObject lifecycle callbacks (init, regStats, 32# etc.) and manages the lifecycle of the systemc simulation accordingly. 33class SystemC_Kernel(SimObject): 34 type = 'SystemC_Kernel' 35 cxx_class = 'sc_gem5::Kernel' 36 cxx_header = 'systemc/core/kernel.hh' --- 20 unchanged lines hidden (view full) --- 57 }) 58 59class SystemC_ScModule(SystemC_ScObject): 60 type = 'SystemC_ScModule' 61 abstract = True 62 cxx_class = 'sc_core::sc_module' 63 cxx_header = 'systemc/ext/core/sc_module.hh' 64 |
65 @cxxMethod(return_value_policy="reference", cxx_name="gem5_getPort") 66 def getPort(self, if_name, iex): 67 return None 68 |
69try: 70 import _m5 71except: 72 pass 73else: 74 import _m5.systemc 75 _m5.systemc.python_ready() |