system.hh (8666:97d873b8b13e) system.hh (8703:f2ac0bca75df)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

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39#include <vector>
40
41#include "base/loader/symtab.hh"
42#include "base/misc.hh"
43#include "base/statistics.hh"
44#include "config/full_system.hh"
45#include "cpu/pc_event.hh"
46#include "enums/MemoryMode.hh"
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;

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51#include <vector>
52
53#include "base/loader/symtab.hh"
54#include "base/misc.hh"
55#include "base/statistics.hh"
56#include "config/full_system.hh"
57#include "cpu/pc_event.hh"
58#include "enums/MemoryMode.hh"
59#include "mem/mem_object.hh"
47#include "mem/port.hh"
48#include "params/System.hh"
60#include "mem/port.hh"
61#include "params/System.hh"
49#include "sim/sim_object.hh"
50
51#if FULL_SYSTEM
52#include "kern/system_events.hh"
53#endif
54
55class BaseCPU;
56class ThreadContext;
57class ObjectFile;
58class PhysicalMemory;
59
60#if FULL_SYSTEM
61class Platform;
62class FunctionalPort;
63class VirtualPort;
64#endif
65class GDBListener;
66class BaseRemoteGDB;
67
62
63#if FULL_SYSTEM
64#include "kern/system_events.hh"
65#endif
66
67class BaseCPU;
68class ThreadContext;
69class ObjectFile;
70class PhysicalMemory;
71
72#if FULL_SYSTEM
73class Platform;
74class FunctionalPort;
75class VirtualPort;
76#endif
77class GDBListener;
78class BaseRemoteGDB;
79
68class System : public SimObject
80class System : public MemObject
69{
81{
82 private:
83
84 /**
85 * Private class for the system port which is only used as a
86 * master for debug access and for non-structural entities that do
87 * not have a port of their own.
88 */
89 class SystemPort : public Port
90 {
91 public:
92
93 /**
94 * Create a system port with a name and an owner.
95 */
96 SystemPort(const std::string &_name, MemObject *_owner)
97 : Port(_name, _owner)
98 { }
99 bool recvTiming(PacketPtr pkt)
100 { panic("SystemPort does not receive timing!\n"); return false; }
101 Tick recvAtomic(PacketPtr pkt)
102 { panic("SystemPort does not receive atomic!\n"); return 0; }
103 void recvFunctional(PacketPtr pkt)
104 { panic("SystemPort does not receive functional!\n"); }
105 void recvStatusChange(Status status) { }
106
107 };
108
109 SystemPort _systemPort;
110
70 public:
71
111 public:
112
113 /**
114 * Get a pointer to the system port that can be used by
115 * non-structural simulation objects like processes or threads, or
116 * external entities like loaders and debuggers, etc, to access
117 * the memory system.
118 *
119 * @return a pointer to the system port we own
120 */
121 Port* getSystemPort() { return &_systemPort; }
122
123 /**
124 * Additional function to return the Port of a memory object.
125 */
126 Port *getPort(const std::string &if_name, int idx = -1);
127
72 static const char *MemoryModeStrings[3];
73
74 Enums::MemoryMode
75 getMemoryMode()
76 {
77 assert(memoryMode);
78 return memoryMode;
79 }

--- 254 unchanged lines hidden --- 		128 static const char *MemoryModeStrings[3];
129
130 Enums::MemoryMode
131 getMemoryMode()
132 {
133 assert(memoryMode);
134 return memoryMode;
135 }

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