system.hh (13883:f44e21d3aaa7) system.hh (13892:0182a0601f66)
1/*
2 * Copyright (c) 2012, 2014, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include <vector>
54
55#include "arch/isa_traits.hh"
56#include "base/loader/symtab.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "enums/MemoryMode.hh"
60#include "mem/mem_master.hh"
1/*
2 * Copyright (c) 2012, 2014, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include <vector>
54
55#include "arch/isa_traits.hh"
56#include "base/loader/symtab.hh"
57#include "base/statistics.hh"
58#include "config/the_isa.hh"
59#include "enums/MemoryMode.hh"
60#include "mem/mem_master.hh"
61#include "mem/mem_object.hh"
62#include "mem/physical.hh"
63#include "mem/port.hh"
64#include "mem/port_proxy.hh"
65#include "params/System.hh"
66#include "sim/futex_map.hh"
67#include "sim/redirect_path.hh"
68#include "sim/se_signal.hh"
61#include "mem/physical.hh"
62#include "mem/port.hh"
63#include "mem/port_proxy.hh"
64#include "params/System.hh"
65#include "sim/futex_map.hh"
66#include "sim/redirect_path.hh"
67#include "sim/se_signal.hh"
68#include "sim/sim_object.hh"
69
70/**
71 * To avoid linking errors with LTO, only include the header if we
72 * actually have the definition.
73 */
74#if THE_ISA != NULL_ISA
75#include "cpu/pc_event.hh"
76
77#endif
78
79class BaseRemoteGDB;
80class KvmVM;
81class ObjectFile;
82class ThreadContext;
83
69
70/**
71 * To avoid linking errors with LTO, only include the header if we
72 * actually have the definition.
73 */
74#if THE_ISA != NULL_ISA
75#include "cpu/pc_event.hh"
76
77#endif
78
79class BaseRemoteGDB;
80class KvmVM;
81class ObjectFile;
82class ThreadContext;
83
84class System : public MemObject
84class System : public SimObject
85{
86 private:
87
88 /**
89 * Private class for the system port which is only used as a
90 * master for debug access and for non-structural entities that do
91 * not have a port of their own.
92 */
93 class SystemPort : public MasterPort
94 {
95 public:
96
97 /**
98 * Create a system port with a name and an owner.
99 */
85{
86 private:
87
88 /**
89 * Private class for the system port which is only used as a
90 * master for debug access and for non-structural entities that do
91 * not have a port of their own.
92 */
93 class SystemPort : public MasterPort
94 {
95 public:
96
97 /**
98 * Create a system port with a name and an owner.
99 */
100 SystemPort(const std::string &_name, MemObject *_owner)
100 SystemPort(const std::string &_name, SimObject *_owner)
101 : MasterPort(_name, _owner)
102 { }
103 bool recvTimingResp(PacketPtr pkt) override
104 { panic("SystemPort does not receive timing!\n"); return false; }
105 void recvReqRetry() override
106 { panic("SystemPort does not expect retry!\n"); }
107 };
108

--- 552 unchanged lines hidden --- 		101 : MasterPort(_name, _owner)
102 { }
103 bool recvTimingResp(PacketPtr pkt) override
104 { panic("SystemPort does not receive timing!\n"); return false; }
105 void recvReqRetry() override
106 { panic("SystemPort does not expect retry!\n"); }
107 };
108

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