1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Lisa Hsu 43 * Nathan Binkert 44 * Rick Strong 45 */ 46 47#ifndef __SYSTEM_HH__ 48#define __SYSTEM_HH__ 49 50#include <string> 51#include <utility> 52#include <vector> 53 54#include "base/loader/symtab.hh" 55#include "base/misc.hh" 56#include "base/statistics.hh" 57#include "cpu/pc_event.hh" 58#include "enums/MemoryMode.hh" 59#include "kern/system_events.hh" 60#include "mem/fs_translating_port_proxy.hh" 61#include "mem/mem_object.hh" 62#include "mem/port.hh" 63#include "mem/physical.hh" 64#include "params/System.hh" 65 66class BaseCPU; 67class BaseRemoteGDB; 68class GDBListener; 69class ObjectFile; 70class Platform; 71class ThreadContext; 72 73class System : public MemObject 74{ 75 private: 76 77 /** 78 * Private class for the system port which is only used as a 79 * master for debug access and for non-structural entities that do 80 * not have a port of their own. 81 */ 82 class SystemPort : public MasterPort 83 { 84 public: 85 86 /** 87 * Create a system port with a name and an owner. 88 */ 89 SystemPort(const std::string &_name, MemObject *_owner) 90 : MasterPort(_name, _owner) 91 { } 92 bool recvTimingResp(PacketPtr pkt) 93 { panic("SystemPort does not receive timing!\n"); return false; } 94 void recvRetry() 95 { panic("SystemPort does not expect retry!\n"); } 96 }; 97 98 SystemPort _systemPort; 99 100 public: 101 102 /** 103 * After all objects have been created and all ports are 104 * connected, check that the system port is connected. 105 */ 106 virtual void init(); 107 108 /** 109 * Get a reference to the system port that can be used by 110 * non-structural simulation objects like processes or threads, or 111 * external entities like loaders and debuggers, etc, to access 112 * the memory system. 113 * 114 * @return a reference to the system port we own 115 */ 116 MasterPort& getSystemPort() { return _systemPort; } 117 118 /** 119 * Additional function to return the Port of a memory object. 120 */ 121 BaseMasterPort& getMasterPort(const std::string &if_name, 122 PortID idx = InvalidPortID); 123 124 static const char *MemoryModeStrings[4]; 125 126 /** @{ */ 127 /** 128 * Is the system in atomic mode? 129 * 130 * There are currently two different atomic memory modes: 131 * 'atomic', which supports caches; and 'atomic_noncaching', which 132 * bypasses caches. The latter is used by hardware virtualized 133 * CPUs. SimObjects are expected to use Port::sendAtomic() and 134 * Port::recvAtomic() when accessing memory in this mode. 135 */ 136 bool isAtomicMode() const { 137 return memoryMode == Enums::atomic || 138 memoryMode == Enums::atomic_noncaching; 139 } 140 141 /** 142 * Is the system in timing mode? 143 * 144 * SimObjects are expected to use Port::sendTiming() and 145 * Port::recvTiming() when accessing memory in this mode. 146 */ 147 bool isTimingMode() const { 148 return memoryMode == Enums::timing; 149 } 150 151 /** 152 * Should caches be bypassed? 153 * 154 * Some CPUs need to bypass caches to allow direct memory 155 * accesses, which is required for hardware virtualization. 156 */ 157 bool bypassCaches() const { 158 return memoryMode == Enums::atomic_noncaching; 159 } 160 /** @} */ 161 162 /** @{ */ 163 /** 164 * Get the memory mode of the system. 165 * 166 * \warn This should only be used by the Python world. The C++ 167 * world should use one of the query functions above 168 * (isAtomicMode(), isTimingMode(), bypassCaches()). 169 */ 170 Enums::MemoryMode getMemoryMode() const { return memoryMode; } 171 172 /** 173 * Change the memory mode of the system. 174 * 175 * \warn This should only be called by the Python! 176 * 177 * @param mode Mode to change to (atomic/timing/...) 178 */ 179 void setMemoryMode(Enums::MemoryMode mode); 180 /** @} */ 181
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182 /** 183 * Get the cache line size of the system. 184 */ 185 unsigned int cacheLineSize() const { return _cacheLineSize; } 186 |
187 PCEventQueue pcEventQueue; 188 189 std::vector<ThreadContext *> threadContexts; 190 int _numContexts; 191 192 ThreadContext *getThreadContext(ThreadID tid) 193 { 194 return threadContexts[tid]; 195 } 196 197 int numContexts() 198 { 199 assert(_numContexts == (int)threadContexts.size()); 200 return _numContexts; 201 } 202 203 /** Return number of running (non-halted) thread contexts in 204 * system. These threads could be Active or Suspended. */ 205 int numRunningContexts(); 206 207 Addr pagePtr; 208 209 uint64_t init_param; 210 211 /** Port to physical memory used for writing object files into ram at 212 * boot.*/ 213 PortProxy physProxy; 214 FSTranslatingPortProxy virtProxy; 215 216 /** kernel symbol table */ 217 SymbolTable *kernelSymtab; 218 219 /** Object pointer for the kernel code */ 220 ObjectFile *kernel; 221 222 /** Begining of kernel code */ 223 Addr kernelStart; 224 225 /** End of kernel code */ 226 Addr kernelEnd; 227 228 /** Entry point in the kernel to start at */ 229 Addr kernelEntry; 230 231 /** Mask that should be anded for binary/symbol loading. 232 * This allows one two different OS requirements for the same ISA to be 233 * handled. Some OSes are compiled for a virtual address and need to be 234 * loaded into physical memory that starts at address 0, while other 235 * bare metal tools generate images that start at address 0. 236 */ 237 Addr loadAddrMask; 238 239 protected: 240 uint64_t nextPID; 241 242 public: 243 uint64_t allocatePID() 244 { 245 return nextPID++; 246 } 247 248 /** Get a pointer to access the physical memory of the system */ 249 PhysicalMemory& getPhysMem() { return physmem; } 250 251 /** Amount of physical memory that is still free */ 252 Addr freeMemSize() const; 253 254 /** Amount of physical memory that exists */ 255 Addr memSize() const; 256 257 /** 258 * Check if a physical address is within a range of a memory that 259 * is part of the global address map. 260 * 261 * @param addr A physical address 262 * @return Whether the address corresponds to a memory 263 */ 264 bool isMemAddr(Addr addr) const; 265 266 protected: 267 268 PhysicalMemory physmem; 269 270 Enums::MemoryMode memoryMode;
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271 272 const unsigned int _cacheLineSize; 273 |
274 uint64_t workItemsBegin; 275 uint64_t workItemsEnd; 276 uint32_t numWorkIds; 277 std::vector<bool> activeCpus; 278 279 /** This array is a per-sytem list of all devices capable of issuing a 280 * memory system request and an associated string for each master id. 281 * It's used to uniquely id any master in the system by name for things 282 * like cache statistics. 283 */ 284 std::vector<std::string> masterIds; 285 286 public: 287 288 /** Request an id used to create a request object in the system. All objects 289 * that intend to issues requests into the memory system must request an id 290 * in the init() phase of startup. All master ids must be fixed by the 291 * regStats() phase that immediately preceeds it. This allows objects in the 292 * memory system to understand how many masters may exist and 293 * appropriately name the bins of their per-master stats before the stats 294 * are finalized 295 */ 296 MasterID getMasterId(std::string req_name); 297 298 /** Get the name of an object for a given request id. 299 */ 300 std::string getMasterName(MasterID master_id); 301 302 /** Get the number of masters registered in the system */ 303 MasterID maxMasters() 304 { 305 return masterIds.size(); 306 } 307 308 virtual void regStats(); 309 /** 310 * Called by pseudo_inst to track the number of work items started by this 311 * system. 312 */ 313 uint64_t 314 incWorkItemsBegin() 315 { 316 return ++workItemsBegin; 317 } 318 319 /** 320 * Called by pseudo_inst to track the number of work items completed by 321 * this system. 322 */ 323 uint64_t 324 incWorkItemsEnd() 325 { 326 return ++workItemsEnd; 327 } 328 329 /** 330 * Called by pseudo_inst to mark the cpus actively executing work items. 331 * Returns the total number of cpus that have executed work item begin or 332 * ends. 333 */ 334 int 335 markWorkItem(int index) 336 { 337 int count = 0; 338 assert(index < activeCpus.size()); 339 activeCpus[index] = true; 340 for (std::vector<bool>::iterator i = activeCpus.begin(); 341 i < activeCpus.end(); i++) { 342 if (*i) count++; 343 } 344 return count; 345 } 346 347 inline void workItemBegin(uint32_t tid, uint32_t workid) 348 { 349 std::pair<uint32_t,uint32_t> p(tid, workid); 350 lastWorkItemStarted[p] = curTick(); 351 } 352 353 void workItemEnd(uint32_t tid, uint32_t workid); 354 355 /** 356 * Fix up an address used to match PCs for hooking simulator 357 * events on to target function executions. See comment in 358 * system.cc for details. 359 */ 360 virtual Addr fixFuncEventAddr(Addr addr) 361 { 362 panic("Base fixFuncEventAddr not implemented.\n"); 363 } 364 365 /** @{ */ 366 /** 367 * Add a function-based event to the given function, to be looked 368 * up in the specified symbol table. 369 * 370 * The ...OrPanic flavor of the method causes the simulator to 371 * panic if the symbol can't be found. 372 * 373 * @param symtab Symbol table to use for look up. 374 * @param lbl Function to hook the event to. 375 * @param desc Description to be passed to the event. 376 * @param args Arguments to be forwarded to the event constructor. 377 */ 378 template <class T, typename... Args> 379 T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 380 const std::string &desc, Args... args) 381 { 382 Addr addr = 0; // initialize only to avoid compiler warning 383 384 if (symtab->findAddress(lbl, addr)) { 385 T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 386 std::forward<Args>(args)...); 387 return ev; 388 } 389 390 return NULL; 391 } 392 393 template <class T> 394 T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 395 { 396 return addFuncEvent<T>(symtab, lbl, lbl); 397 } 398 399 template <class T, typename... Args> 400 T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 401 Args... args) 402 { 403 T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 404 if (!e) 405 panic("Failed to find symbol '%s'", lbl); 406 return e; 407 } 408 /** @} */ 409 410 /** @{ */ 411 /** 412 * Add a function-based event to a kernel symbol. 413 * 414 * These functions work like their addFuncEvent() and 415 * addFuncEventOrPanic() counterparts. The only difference is that 416 * they automatically use the kernel symbol table. All arguments 417 * are forwarded to the underlying method. 418 * 419 * @see addFuncEvent() 420 * @see addFuncEventOrPanic() 421 * 422 * @param lbl Function to hook the event to. 423 * @param args Arguments to be passed to addFuncEvent 424 */ 425 template <class T, typename... Args> 426 T *addKernelFuncEvent(const char *lbl, Args... args) 427 { 428 return addFuncEvent<T>(kernelSymtab, lbl, 429 std::forward<Args>(args)...); 430 } 431 432 template <class T, typename... Args> 433 T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 434 { 435 T *e(addFuncEvent<T>(kernelSymtab, lbl, 436 std::forward<Args>(args)...)); 437 if (!e) 438 panic("Failed to find kernel symbol '%s'", lbl); 439 return e; 440 } 441 /** @} */ 442 443 public: 444 std::vector<BaseRemoteGDB *> remoteGDB; 445 std::vector<GDBListener *> gdbListen; 446 bool breakpoint(); 447 448 public: 449 typedef SystemParams Params; 450 451 protected: 452 Params *_params; 453 454 public: 455 System(Params *p); 456 ~System(); 457 458 void initState(); 459 460 const Params *params() const { return (const Params *)_params; } 461 462 public: 463 464 /** 465 * Returns the addess the kernel starts at. 466 * @return address the kernel starts at 467 */ 468 Addr getKernelStart() const { return kernelStart; } 469 470 /** 471 * Returns the addess the kernel ends at. 472 * @return address the kernel ends at 473 */ 474 Addr getKernelEnd() const { return kernelEnd; } 475 476 /** 477 * Returns the addess the entry point to the kernel code. 478 * @return entry point of the kernel code 479 */ 480 Addr getKernelEntry() const { return kernelEntry; } 481 482 /// Allocate npages contiguous unused physical pages 483 /// @return Starting address of first page 484 Addr allocPhysPages(int npages); 485 486 int registerThreadContext(ThreadContext *tc, int assigned=-1); 487 void replaceThreadContext(ThreadContext *tc, int context_id); 488 489 void serialize(std::ostream &os); 490 void unserialize(Checkpoint *cp, const std::string §ion); 491 492 unsigned int drain(DrainManager *dm); 493 void drainResume(); 494 495 public: 496 Counter totalNumInsts; 497 EventQueue instEventQueue; 498 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 499 std::map<uint32_t, Stats::Histogram*> workItemStats; 500 501 //////////////////////////////////////////// 502 // 503 // STATIC GLOBAL SYSTEM LIST 504 // 505 //////////////////////////////////////////// 506 507 static std::vector<System *> systemList; 508 static int numSystemsRunning; 509 510 static void printSystems(); 511 512 // For futex system call 513 std::map<uint64_t, std::list<ThreadContext *> * > futexMap; 514 515 protected: 516 517 /** 518 * If needed, serialize additional symbol table entries for a 519 * specific subclass of this sytem. Currently this is used by 520 * Alpha and MIPS. 521 * 522 * @param os stream to serialize to 523 */ 524 virtual void serializeSymtab(std::ostream &os) {} 525 526 /** 527 * If needed, unserialize additional symbol table entries for a 528 * specific subclass of this system. 529 * 530 * @param cp checkpoint to unserialize from 531 * @param section relevant section in the checkpoint 532 */ 533 virtual void unserializeSymtab(Checkpoint *cp, 534 const std::string §ion) {} 535 536}; 537 538void printSystems(); 539 540#endif // __SYSTEM_HH__
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