1/* 2 * Copyright (c) 2012, 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan 15 * Copyright (c) 2011 Regents of the University of California 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 * Lisa Hsu 43 * Nathan Binkert 44 * Rick Strong 45 */ 46 47#ifndef __SYSTEM_HH__ 48#define __SYSTEM_HH__ 49 50#include <string> 51#include <unordered_map> 52#include <utility> 53#include <vector> 54 55#include "arch/isa_traits.hh" 56#include "base/loader/symtab.hh" 57#include "base/statistics.hh" 58#include "config/the_isa.hh" 59#include "enums/MemoryMode.hh" 60#include "mem/mem_object.hh" 61#include "mem/physical.hh" 62#include "mem/port.hh" 63#include "mem/port_proxy.hh" 64#include "params/System.hh" 65#include "sim/futex_map.hh" 66#include "sim/se_signal.hh" 67 68/** 69 * To avoid linking errors with LTO, only include the header if we 70 * actually have the definition. 71 */ 72#if THE_ISA != NULL_ISA 73#include "cpu/pc_event.hh" 74 75#endif 76 77class BaseRemoteGDB; |
78class KvmVM; 79class ObjectFile; 80class ThreadContext; 81 82class System : public MemObject 83{ 84 private: 85 86 /** 87 * Private class for the system port which is only used as a 88 * master for debug access and for non-structural entities that do 89 * not have a port of their own. 90 */ 91 class SystemPort : public MasterPort 92 { 93 public: 94 95 /** 96 * Create a system port with a name and an owner. 97 */ 98 SystemPort(const std::string &_name, MemObject *_owner) 99 : MasterPort(_name, _owner) 100 { } 101 bool recvTimingResp(PacketPtr pkt) override 102 { panic("SystemPort does not receive timing!\n"); return false; } 103 void recvReqRetry() override 104 { panic("SystemPort does not expect retry!\n"); } 105 }; 106 107 SystemPort _systemPort; 108 109 public: 110 111 /** 112 * After all objects have been created and all ports are 113 * connected, check that the system port is connected. 114 */ 115 void init() override; 116 117 /** 118 * Get a reference to the system port that can be used by 119 * non-structural simulation objects like processes or threads, or 120 * external entities like loaders and debuggers, etc, to access 121 * the memory system. 122 * 123 * @return a reference to the system port we own 124 */ 125 MasterPort& getSystemPort() { return _systemPort; } 126 127 /** 128 * Additional function to return the Port of a memory object. 129 */ 130 BaseMasterPort& getMasterPort(const std::string &if_name, 131 PortID idx = InvalidPortID) override; 132 133 /** @{ */ 134 /** 135 * Is the system in atomic mode? 136 * 137 * There are currently two different atomic memory modes: 138 * 'atomic', which supports caches; and 'atomic_noncaching', which 139 * bypasses caches. The latter is used by hardware virtualized 140 * CPUs. SimObjects are expected to use Port::sendAtomic() and 141 * Port::recvAtomic() when accessing memory in this mode. 142 */ 143 bool isAtomicMode() const { 144 return memoryMode == Enums::atomic || 145 memoryMode == Enums::atomic_noncaching; 146 } 147 148 /** 149 * Is the system in timing mode? 150 * 151 * SimObjects are expected to use Port::sendTiming() and 152 * Port::recvTiming() when accessing memory in this mode. 153 */ 154 bool isTimingMode() const { 155 return memoryMode == Enums::timing; 156 } 157 158 /** 159 * Should caches be bypassed? 160 * 161 * Some CPUs need to bypass caches to allow direct memory 162 * accesses, which is required for hardware virtualization. 163 */ 164 bool bypassCaches() const { 165 return memoryMode == Enums::atomic_noncaching; 166 } 167 /** @} */ 168 169 /** @{ */ 170 /** 171 * Get the memory mode of the system. 172 * 173 * \warn This should only be used by the Python world. The C++ 174 * world should use one of the query functions above 175 * (isAtomicMode(), isTimingMode(), bypassCaches()). 176 */ 177 Enums::MemoryMode getMemoryMode() const { return memoryMode; } 178 179 /** 180 * Change the memory mode of the system. 181 * 182 * \warn This should only be called by the Python! 183 * 184 * @param mode Mode to change to (atomic/timing/...) 185 */ 186 void setMemoryMode(Enums::MemoryMode mode); 187 /** @} */ 188 189 /** 190 * Get the cache line size of the system. 191 */ 192 unsigned int cacheLineSize() const { return _cacheLineSize; } 193 194#if THE_ISA != NULL_ISA 195 PCEventQueue pcEventQueue; 196#endif 197 198 std::vector<ThreadContext *> threadContexts; 199 int _numContexts; 200 const bool multiThread; 201 202 ThreadContext *getThreadContext(ContextID tid) 203 { 204 return threadContexts[tid]; 205 } 206 207 int numContexts() 208 { 209 assert(_numContexts == (int)threadContexts.size()); 210 return _numContexts; 211 } 212 213 /** Return number of running (non-halted) thread contexts in 214 * system. These threads could be Active or Suspended. */ 215 int numRunningContexts(); 216 217 Addr pagePtr; 218 219 uint64_t init_param; 220 221 /** Port to physical memory used for writing object files into ram at 222 * boot.*/ 223 PortProxy physProxy; 224 225 /** kernel symbol table */ 226 SymbolTable *kernelSymtab; 227 228 /** Object pointer for the kernel code */ 229 ObjectFile *kernel; 230 231 /** Additional object files */ 232 std::vector<ObjectFile *> kernelExtras; 233 234 /** Beginning of kernel code */ 235 Addr kernelStart; 236 237 /** End of kernel code */ 238 Addr kernelEnd; 239 240 /** Entry point in the kernel to start at */ 241 Addr kernelEntry; 242 243 /** Mask that should be anded for binary/symbol loading. 244 * This allows one two different OS requirements for the same ISA to be 245 * handled. Some OSes are compiled for a virtual address and need to be 246 * loaded into physical memory that starts at address 0, while other 247 * bare metal tools generate images that start at address 0. 248 */ 249 Addr loadAddrMask; 250 251 /** Offset that should be used for binary/symbol loading. 252 * This further allows more flexibility than the loadAddrMask allows alone 253 * in loading kernels and similar. The loadAddrOffset is applied after the 254 * loadAddrMask. 255 */ 256 Addr loadAddrOffset; 257 258 public: 259 /** 260 * Get a pointer to the Kernel Virtual Machine (KVM) SimObject, 261 * if present. 262 */ 263 KvmVM* getKvmVM() { 264 return kvmVM; 265 } 266 267 /** Verify gem5 configuration will support KVM emulation */ 268 bool validKvmEnvironment() const; 269 270 /** Get a pointer to access the physical memory of the system */ 271 PhysicalMemory& getPhysMem() { return physmem; } 272 273 /** Amount of physical memory that is still free */ 274 Addr freeMemSize() const; 275 276 /** Amount of physical memory that exists */ 277 Addr memSize() const; 278 279 /** 280 * Check if a physical address is within a range of a memory that 281 * is part of the global address map. 282 * 283 * @param addr A physical address 284 * @return Whether the address corresponds to a memory 285 */ 286 bool isMemAddr(Addr addr) const; 287 288 /** 289 * Get the architecture. 290 */ 291 Arch getArch() const { return Arch::TheISA; } 292 293 /** 294 * Get the page bytes for the ISA. 295 */ 296 Addr getPageBytes() const { return TheISA::PageBytes; } 297 298 /** 299 * Get the number of bits worth of in-page address for the ISA. 300 */ 301 Addr getPageShift() const { return TheISA::PageShift; } 302 303 /** 304 * The thermal model used for this system (if any). 305 */ 306 ThermalModel * getThermalModel() const { return thermalModel; } 307 308 protected: 309 310 KvmVM *const kvmVM; 311 312 PhysicalMemory physmem; 313 314 Enums::MemoryMode memoryMode; 315 316 const unsigned int _cacheLineSize; 317 318 uint64_t workItemsBegin; 319 uint64_t workItemsEnd; 320 uint32_t numWorkIds; 321 std::vector<bool> activeCpus; 322 323 /** This array is a per-system list of all devices capable of issuing a 324 * memory system request and an associated string for each master id. 325 * It's used to uniquely id any master in the system by name for things 326 * like cache statistics. 327 */ 328 std::vector<std::string> masterIds; 329 330 ThermalModel * thermalModel; 331 332 public: 333 334 /** Request an id used to create a request object in the system. All objects 335 * that intend to issues requests into the memory system must request an id 336 * in the init() phase of startup. All master ids must be fixed by the 337 * regStats() phase that immediately precedes it. This allows objects in 338 * the memory system to understand how many masters may exist and 339 * appropriately name the bins of their per-master stats before the stats 340 * are finalized 341 */ 342 MasterID getMasterId(std::string req_name); 343 344 /** Get the name of an object for a given request id. 345 */ 346 std::string getMasterName(MasterID master_id); 347 348 /** Get the number of masters registered in the system */ 349 MasterID maxMasters() 350 { 351 return masterIds.size(); 352 } 353 354 void regStats() override; 355 /** 356 * Called by pseudo_inst to track the number of work items started by this 357 * system. 358 */ 359 uint64_t 360 incWorkItemsBegin() 361 { 362 return ++workItemsBegin; 363 } 364 365 /** 366 * Called by pseudo_inst to track the number of work items completed by 367 * this system. 368 */ 369 uint64_t 370 incWorkItemsEnd() 371 { 372 return ++workItemsEnd; 373 } 374 375 /** 376 * Called by pseudo_inst to mark the cpus actively executing work items. 377 * Returns the total number of cpus that have executed work item begin or 378 * ends. 379 */ 380 int 381 markWorkItem(int index) 382 { 383 int count = 0; 384 assert(index < activeCpus.size()); 385 activeCpus[index] = true; 386 for (std::vector<bool>::iterator i = activeCpus.begin(); 387 i < activeCpus.end(); i++) { 388 if (*i) count++; 389 } 390 return count; 391 } 392 393 inline void workItemBegin(uint32_t tid, uint32_t workid) 394 { 395 std::pair<uint32_t,uint32_t> p(tid, workid); 396 lastWorkItemStarted[p] = curTick(); 397 } 398 399 void workItemEnd(uint32_t tid, uint32_t workid); 400 401 /** 402 * Fix up an address used to match PCs for hooking simulator 403 * events on to target function executions. See comment in 404 * system.cc for details. 405 */ 406 virtual Addr fixFuncEventAddr(Addr addr) 407 { 408 panic("Base fixFuncEventAddr not implemented.\n"); 409 } 410 411 /** @{ */ 412 /** 413 * Add a function-based event to the given function, to be looked 414 * up in the specified symbol table. 415 * 416 * The ...OrPanic flavor of the method causes the simulator to 417 * panic if the symbol can't be found. 418 * 419 * @param symtab Symbol table to use for look up. 420 * @param lbl Function to hook the event to. 421 * @param desc Description to be passed to the event. 422 * @param args Arguments to be forwarded to the event constructor. 423 */ 424 template <class T, typename... Args> 425 T *addFuncEvent(const SymbolTable *symtab, const char *lbl, 426 const std::string &desc, Args... args) 427 { 428 Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning 429 430#if THE_ISA != NULL_ISA 431 if (symtab->findAddress(lbl, addr)) { 432 T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr), 433 std::forward<Args>(args)...); 434 return ev; 435 } 436#endif 437 438 return NULL; 439 } 440 441 template <class T> 442 T *addFuncEvent(const SymbolTable *symtab, const char *lbl) 443 { 444 return addFuncEvent<T>(symtab, lbl, lbl); 445 } 446 447 template <class T, typename... Args> 448 T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl, 449 Args... args) 450 { 451 T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...)); 452 if (!e) 453 panic("Failed to find symbol '%s'", lbl); 454 return e; 455 } 456 /** @} */ 457 458 /** @{ */ 459 /** 460 * Add a function-based event to a kernel symbol. 461 * 462 * These functions work like their addFuncEvent() and 463 * addFuncEventOrPanic() counterparts. The only difference is that 464 * they automatically use the kernel symbol table. All arguments 465 * are forwarded to the underlying method. 466 * 467 * @see addFuncEvent() 468 * @see addFuncEventOrPanic() 469 * 470 * @param lbl Function to hook the event to. 471 * @param args Arguments to be passed to addFuncEvent 472 */ 473 template <class T, typename... Args> 474 T *addKernelFuncEvent(const char *lbl, Args... args) 475 { 476 return addFuncEvent<T>(kernelSymtab, lbl, 477 std::forward<Args>(args)...); 478 } 479 480 template <class T, typename... Args> 481 T *addKernelFuncEventOrPanic(const char *lbl, Args... args) 482 { 483 T *e(addFuncEvent<T>(kernelSymtab, lbl, 484 std::forward<Args>(args)...)); 485 if (!e) 486 panic("Failed to find kernel symbol '%s'", lbl); 487 return e; 488 } 489 /** @} */ 490 491 public: 492 std::vector<BaseRemoteGDB *> remoteGDB; |
493 bool breakpoint(); 494 495 public: 496 typedef SystemParams Params; 497 498 protected: 499 Params *_params; 500 501 public: 502 System(Params *p); 503 ~System(); 504 505 void initState() override; 506 507 const Params *params() const { return (const Params *)_params; } 508 509 public: 510 511 /** 512 * Returns the address the kernel starts at. 513 * @return address the kernel starts at 514 */ 515 Addr getKernelStart() const { return kernelStart; } 516 517 /** 518 * Returns the address the kernel ends at. 519 * @return address the kernel ends at 520 */ 521 Addr getKernelEnd() const { return kernelEnd; } 522 523 /** 524 * Returns the address the entry point to the kernel code. 525 * @return entry point of the kernel code 526 */ 527 Addr getKernelEntry() const { return kernelEntry; } 528 529 /// Allocate npages contiguous unused physical pages 530 /// @return Starting address of first page 531 Addr allocPhysPages(int npages); 532 533 ContextID registerThreadContext(ThreadContext *tc, 534 ContextID assigned = InvalidContextID); 535 void replaceThreadContext(ThreadContext *tc, ContextID context_id); 536 537 void serialize(CheckpointOut &cp) const override; 538 void unserialize(CheckpointIn &cp) override; 539 540 void drainResume() override; 541 542 public: 543 Counter totalNumInsts; 544 EventQueue instEventQueue; 545 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted; 546 std::map<uint32_t, Stats::Histogram*> workItemStats; 547 548 //////////////////////////////////////////// 549 // 550 // STATIC GLOBAL SYSTEM LIST 551 // 552 //////////////////////////////////////////// 553 554 static std::vector<System *> systemList; 555 static int numSystemsRunning; 556 557 static void printSystems(); 558 559 FutexMap futexMap; 560 561 static const int maxPID = 32768; 562 563 /** Process set to track which PIDs have already been allocated */ 564 std::set<int> PIDs; 565 566 // By convention, all signals are owned by the receiving process. The 567 // receiver will delete the signal upon reception. 568 std::list<BasicSignal> signalList; 569 570 protected: 571 572 /** 573 * If needed, serialize additional symbol table entries for a 574 * specific subclass of this system. Currently this is used by 575 * Alpha and MIPS. 576 * 577 * @param os stream to serialize to 578 */ 579 virtual void serializeSymtab(CheckpointOut &os) const {} 580 581 /** 582 * If needed, unserialize additional symbol table entries for a 583 * specific subclass of this system. 584 * 585 * @param cp checkpoint to unserialize from 586 * @param section relevant section in the checkpoint 587 */ 588 virtual void unserializeSymtab(CheckpointIn &cp) {} 589 590}; 591 592void printSystems(); 593 594#endif // __SYSTEM_HH__ |