1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Regents of the University of California
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;

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39#include <vector>
40
41#include "base/loader/symtab.hh"
42#include "base/misc.hh"
43#include "base/statistics.hh"
44#include "config/full_system.hh"
45#include "cpu/pc_event.hh"
46#include "enums/MemoryMode.hh"
59#include "mem/mem_object.hh"
47#include "mem/port.hh"
48#include "params/System.hh"
49#include "sim/sim_object.hh"
50
51#if FULL_SYSTEM
52#include "kern/system_events.hh"
53#endif
54
55class BaseCPU;
56class ThreadContext;
57class ObjectFile;
58class PhysicalMemory;
59
60#if FULL_SYSTEM
61class Platform;
74class PortProxy;
75class FSTranslatingPortProxy;
62class FunctionalPort;
63class VirtualPort;
64#endif
65class GDBListener;
66class BaseRemoteGDB;
67
80class System : public MemObject
68class System : public SimObject
69{
82 private:
83
84 /**
85 * Private class for the system port which is only used as a
86 * master for debug access and for non-structural entities that do
87 * not have a port of their own.
88 */
89 class SystemPort : public Port
90 {
91 public:
92
93 /**
94 * Create a system port with a name and an owner.
95 */
96 SystemPort(const std::string &_name, MemObject *_owner)
97 : Port(_name, _owner)
98 { }
99 bool recvTiming(PacketPtr pkt)
100 { panic("SystemPort does not receive timing!\n"); return false; }
101 Tick recvAtomic(PacketPtr pkt)
102 { panic("SystemPort does not receive atomic!\n"); return 0; }
103 void recvFunctional(PacketPtr pkt)
104 { panic("SystemPort does not receive functional!\n"); }
105
106 /**
107 * The system port is a master port connected to a single
108 * slave and thus do not care about what ranges the slave
109 * covers (as there is nothing to choose from).
110 */
111 void recvRangeChange() { }
112
113 };
114
115 SystemPort _systemPort;
116
70 public:
71
119 /**
120 * After all objects have been created and all ports are
121 * connected, check that the system port is connected.
122 */
123 virtual void init();
124
125 /**
126 * Get a pointer to the system port that can be used by
127 * non-structural simulation objects like processes or threads, or
128 * external entities like loaders and debuggers, etc, to access
129 * the memory system.
130 *
131 * @return a pointer to the system port we own
132 */
133 Port* getSystemPort() { return &_systemPort; }
134
135 /**
136 * Additional function to return the Port of a memory object.
137 */
138 Port *getPort(const std::string &if_name, int idx = -1);
139
72 static const char *MemoryModeStrings[3];
73
74 Enums::MemoryMode
75 getMemoryMode()
76 {
77 assert(memoryMode);
78 return memoryMode;
79 }

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109 AddrRangeList memRanges;
110
111 /** check if an address points to valid system memory
112 * and thus we can fetch instructions out of it
113 */
114 bool isMemory(const Addr addr) const;
115
116#if FULL_SYSTEM
185 Platform *platform;
117 uint64_t init_param;
118
119 /** Port to physical memory used for writing object files into ram at
120 * boot.*/
190 PortProxy* physProxy;
191 FSTranslatingPortProxy* virtProxy;
121 FunctionalPort *functionalPort;
122 VirtualPort *virtPort;
123
124 /** kernel symbol table */
125 SymbolTable *kernelSymtab;
126
127 /** Object pointer for the kernel code */
128 ObjectFile *kernel;
129
130 /** Begining of kernel code */

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165
166
167#endif // FULL_SYSTEM
168
169 protected:
170 Enums::MemoryMode memoryMode;
171 uint64_t workItemsBegin;
172 uint64_t workItemsEnd;
242 uint32_t numWorkIds;
173 std::vector<bool> activeCpus;
174
175 public:
246 virtual void regStats();
176 /**
177 * Called by pseudo_inst to track the number of work items started by this
178 * system.
179 */
251 uint64_t
180 uint64_t
181 incWorkItemsBegin()
182 {
183 return ++workItemsBegin;
184 }
185
186 /**
187 * Called by pseudo_inst to track the number of work items completed by
188 * this system.

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206 activeCpus[index] = true;
207 for (std::vector<bool>::iterator i = activeCpus.begin();
208 i < activeCpus.end(); i++) {
209 if (*i) count++;
210 }
211 return count;
212 }
213
285 inline void workItemBegin(uint32_t tid, uint32_t workid)
286 {
287 std::pair<uint32_t,uint32_t> p(tid, workid);
288 lastWorkItemStarted[p] = curTick();
289 }
290
291 void workItemEnd(uint32_t tid, uint32_t workid);
292
214#if FULL_SYSTEM
215 /**
216 * Fix up an address used to match PCs for hooking simulator
217 * events on to target function executions. See comment in
218 * system.cc for details.
219 */
220 virtual Addr fixFuncEventAddr(Addr addr) = 0;
221

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281 /**
282 * Returns the addess the entry point to the kernel code.
283 * @return entry point of the kernel code
284 */
285 Addr getKernelEntry() const { return kernelEntry; }
286
287#else
288
368 /// Allocate npages contiguous unused physical pages
369 /// @return Starting address of first page
370 Addr allocPhysPages(int npages);
289 Addr new_page();
290
291#endif // FULL_SYSTEM
292
293 int registerThreadContext(ThreadContext *tc, int assigned=-1);
294 void replaceThreadContext(ThreadContext *tc, int context_id);
295
296 void serialize(std::ostream &os);
297 void unserialize(Checkpoint *cp, const std::string &section);
298 virtual void resume();
299
300 public:
301 Counter totalNumInsts;
302 EventQueue instEventQueue;
384 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted;
385 std::map<uint32_t, Stats::Histogram*> workItemStats;
303
304 ////////////////////////////////////////////
305 //
306 // STATIC GLOBAL SYSTEM LIST
307 //
308 ////////////////////////////////////////////
309
310 static std::vector<System *> systemList;
311 static int numSystemsRunning;
312
313 static void printSystems();
314
315
316};
317
318#endif // __SYSTEM_HH__