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< * Copyright (c) 2012 ARM Limited
< * All rights reserved
< *
< * The license below extends only to copyright in the software and shall
< * not be construed as granting a license to any other intellectual
< * property including but not limited to intellectual property relating
< * to a hardware implementation of the functionality of the software
< * licensed hereunder. You may use the software subject to the license
< * terms below provided that you ensure that this notice is replicated
< * unmodified and in its entirety in all distributions of the software,
< * modified or unmodified, in source code or in binary form.
< *
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< #include "mem/mem_object.hh"
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> #include "sim/sim_object.hh"
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< class PortProxy;
< class FSTranslatingPortProxy;
---
> class FunctionalPort;
> class VirtualPort;
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< class System : public MemObject
---
> class System : public SimObject
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< private:
<
< /**
< * Private class for the system port which is only used as a
< * master for debug access and for non-structural entities that do
< * not have a port of their own.
< */
< class SystemPort : public Port
< {
< public:
<
< /**
< * Create a system port with a name and an owner.
< */
< SystemPort(const std::string &_name, MemObject *_owner)
< : Port(_name, _owner)
< { }
< bool recvTiming(PacketPtr pkt)
< { panic("SystemPort does not receive timing!\n"); return false; }
< Tick recvAtomic(PacketPtr pkt)
< { panic("SystemPort does not receive atomic!\n"); return 0; }
< void recvFunctional(PacketPtr pkt)
< { panic("SystemPort does not receive functional!\n"); }
<
< /**
< * The system port is a master port connected to a single
< * slave and thus do not care about what ranges the slave
< * covers (as there is nothing to choose from).
< */
< void recvRangeChange() { }
<
< };
<
< SystemPort _systemPort;
<
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< /**
< * After all objects have been created and all ports are
< * connected, check that the system port is connected.
< */
< virtual void init();
<
< /**
< * Get a pointer to the system port that can be used by
< * non-structural simulation objects like processes or threads, or
< * external entities like loaders and debuggers, etc, to access
< * the memory system.
< *
< * @return a pointer to the system port we own
< */
< Port* getSystemPort() { return &_systemPort; }
<
< /**
< * Additional function to return the Port of a memory object.
< */
< Port *getPort(const std::string &if_name, int idx = -1);
<
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< Platform *platform;
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< PortProxy* physProxy;
< FSTranslatingPortProxy* virtProxy;
---
> FunctionalPort *functionalPort;
> VirtualPort *virtPort;
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< uint32_t numWorkIds;
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< virtual void regStats();
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< uint64_t
---
> uint64_t
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< inline void workItemBegin(uint32_t tid, uint32_t workid)
< {
< std::pair<uint32_t,uint32_t> p(tid, workid);
< lastWorkItemStarted[p] = curTick();
< }
<
< void workItemEnd(uint32_t tid, uint32_t workid);
<
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< /// Allocate npages contiguous unused physical pages
< /// @return Starting address of first page
< Addr allocPhysPages(int npages);
---
> Addr new_page();
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< std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted;
< std::map<uint32_t, Stats::Histogram*> workItemStats;