1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Lisa Hsu
43 * Nathan Binkert
44 * Rick Strong
45 */
46
47#ifndef __SYSTEM_HH__
48#define __SYSTEM_HH__
49
50#include <string>
51#include <utility>
52#include <vector>
53
54#include "base/loader/symtab.hh"
55#include "base/misc.hh"
56#include "base/statistics.hh"
57#include "cpu/pc_event.hh"
58#include "enums/MemoryMode.hh"
59#include "kern/system_events.hh"
60#include "mem/mem_object.hh"
61#include "mem/port.hh"
62#include "mem/port_proxy.hh"
63#include "mem/physical.hh"
64#include "params/System.hh"
65
66class BaseCPU;
67class BaseRemoteGDB;
68class GDBListener;
69class ObjectFile;
70class Platform;
71class ThreadContext;
72
73class System : public MemObject
74{
75 private:
76
77 /**
78 * Private class for the system port which is only used as a
79 * master for debug access and for non-structural entities that do
80 * not have a port of their own.
81 */
82 class SystemPort : public MasterPort
83 {
84 public:
85
86 /**
87 * Create a system port with a name and an owner.
88 */
89 SystemPort(const std::string &_name, MemObject *_owner)
90 : MasterPort(_name, _owner)
91 { }
92 bool recvTimingResp(PacketPtr pkt)
93 { panic("SystemPort does not receive timing!\n"); return false; }
94 void recvRetry()
95 { panic("SystemPort does not expect retry!\n"); }
96 };
97
98 SystemPort _systemPort;
99
100 public:
101
102 /**
103 * After all objects have been created and all ports are
104 * connected, check that the system port is connected.
105 */
106 virtual void init();
107
108 /**
109 * Get a reference to the system port that can be used by
110 * non-structural simulation objects like processes or threads, or
111 * external entities like loaders and debuggers, etc, to access
112 * the memory system.
113 *
114 * @return a reference to the system port we own
115 */
116 MasterPort& getSystemPort() { return _systemPort; }
117
118 /**
119 * Additional function to return the Port of a memory object.
120 */
121 BaseMasterPort& getMasterPort(const std::string &if_name,
122 PortID idx = InvalidPortID);
123
124 static const char *MemoryModeStrings[4];
125
126 /** @{ */
127 /**
128 * Is the system in atomic mode?
129 *
130 * There are currently two different atomic memory modes:
131 * 'atomic', which supports caches; and 'atomic_noncaching', which
132 * bypasses caches. The latter is used by hardware virtualized
133 * CPUs. SimObjects are expected to use Port::sendAtomic() and
134 * Port::recvAtomic() when accessing memory in this mode.
135 */
136 bool isAtomicMode() const {
137 return memoryMode == Enums::atomic ||
138 memoryMode == Enums::atomic_noncaching;
139 }
140
141 /**
142 * Is the system in timing mode?
143 *
144 * SimObjects are expected to use Port::sendTiming() and
145 * Port::recvTiming() when accessing memory in this mode.
146 */
147 bool isTimingMode() const {
148 return memoryMode == Enums::timing;
149 }
150
151 /**
152 * Should caches be bypassed?
153 *
154 * Some CPUs need to bypass caches to allow direct memory
155 * accesses, which is required for hardware virtualization.
156 */
157 bool bypassCaches() const {
158 return memoryMode == Enums::atomic_noncaching;
159 }
160 /** @} */
161
162 /** @{ */
163 /**
164 * Get the memory mode of the system.
165 *
166 * \warn This should only be used by the Python world. The C++
167 * world should use one of the query functions above
168 * (isAtomicMode(), isTimingMode(), bypassCaches()).
169 */
170 Enums::MemoryMode getMemoryMode() const { return memoryMode; }
171
172 /**
173 * Change the memory mode of the system.
174 *
175 * \warn This should only be called by the Python!
176 *
177 * @param mode Mode to change to (atomic/timing/...)
178 */
179 void setMemoryMode(Enums::MemoryMode mode);
180 /** @} */
181
182 /**
183 * Get the cache line size of the system.
184 */
185 unsigned int cacheLineSize() const { return _cacheLineSize; }
186
187#if THE_ISA != NULL_ISA
188 PCEventQueue pcEventQueue;
189#endif
190
191 std::vector<ThreadContext *> threadContexts;
192 int _numContexts;
193
194 ThreadContext *getThreadContext(ThreadID tid)
195 {
196 return threadContexts[tid];
197 }
198
199 int numContexts()
200 {
201 assert(_numContexts == (int)threadContexts.size());
202 return _numContexts;
203 }
204
205 /** Return number of running (non-halted) thread contexts in
206 * system. These threads could be Active or Suspended. */
207 int numRunningContexts();
208
209 Addr pagePtr;
210
211 uint64_t init_param;
212
213 /** Port to physical memory used for writing object files into ram at
214 * boot.*/
215 PortProxy physProxy;
216
217 /** kernel symbol table */
218 SymbolTable *kernelSymtab;
219
220 /** Object pointer for the kernel code */
221 ObjectFile *kernel;
222
223 /** Begining of kernel code */
224 Addr kernelStart;
225
226 /** End of kernel code */
227 Addr kernelEnd;
228
229 /** Entry point in the kernel to start at */
230 Addr kernelEntry;
231
232 /** Mask that should be anded for binary/symbol loading.
233 * This allows one two different OS requirements for the same ISA to be
234 * handled. Some OSes are compiled for a virtual address and need to be
235 * loaded into physical memory that starts at address 0, while other
236 * bare metal tools generate images that start at address 0.
237 */
238 Addr loadAddrMask;
239
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2011 Regents of the University of California
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Lisa Hsu
43 * Nathan Binkert
44 * Rick Strong
45 */
46
47#ifndef __SYSTEM_HH__
48#define __SYSTEM_HH__
49
50#include <string>
51#include <utility>
52#include <vector>
53
54#include "base/loader/symtab.hh"
55#include "base/misc.hh"
56#include "base/statistics.hh"
57#include "cpu/pc_event.hh"
58#include "enums/MemoryMode.hh"
59#include "kern/system_events.hh"
60#include "mem/mem_object.hh"
61#include "mem/port.hh"
62#include "mem/port_proxy.hh"
63#include "mem/physical.hh"
64#include "params/System.hh"
65
66class BaseCPU;
67class BaseRemoteGDB;
68class GDBListener;
69class ObjectFile;
70class Platform;
71class ThreadContext;
72
73class System : public MemObject
74{
75 private:
76
77 /**
78 * Private class for the system port which is only used as a
79 * master for debug access and for non-structural entities that do
80 * not have a port of their own.
81 */
82 class SystemPort : public MasterPort
83 {
84 public:
85
86 /**
87 * Create a system port with a name and an owner.
88 */
89 SystemPort(const std::string &_name, MemObject *_owner)
90 : MasterPort(_name, _owner)
91 { }
92 bool recvTimingResp(PacketPtr pkt)
93 { panic("SystemPort does not receive timing!\n"); return false; }
94 void recvRetry()
95 { panic("SystemPort does not expect retry!\n"); }
96 };
97
98 SystemPort _systemPort;
99
100 public:
101
102 /**
103 * After all objects have been created and all ports are
104 * connected, check that the system port is connected.
105 */
106 virtual void init();
107
108 /**
109 * Get a reference to the system port that can be used by
110 * non-structural simulation objects like processes or threads, or
111 * external entities like loaders and debuggers, etc, to access
112 * the memory system.
113 *
114 * @return a reference to the system port we own
115 */
116 MasterPort& getSystemPort() { return _systemPort; }
117
118 /**
119 * Additional function to return the Port of a memory object.
120 */
121 BaseMasterPort& getMasterPort(const std::string &if_name,
122 PortID idx = InvalidPortID);
123
124 static const char *MemoryModeStrings[4];
125
126 /** @{ */
127 /**
128 * Is the system in atomic mode?
129 *
130 * There are currently two different atomic memory modes:
131 * 'atomic', which supports caches; and 'atomic_noncaching', which
132 * bypasses caches. The latter is used by hardware virtualized
133 * CPUs. SimObjects are expected to use Port::sendAtomic() and
134 * Port::recvAtomic() when accessing memory in this mode.
135 */
136 bool isAtomicMode() const {
137 return memoryMode == Enums::atomic ||
138 memoryMode == Enums::atomic_noncaching;
139 }
140
141 /**
142 * Is the system in timing mode?
143 *
144 * SimObjects are expected to use Port::sendTiming() and
145 * Port::recvTiming() when accessing memory in this mode.
146 */
147 bool isTimingMode() const {
148 return memoryMode == Enums::timing;
149 }
150
151 /**
152 * Should caches be bypassed?
153 *
154 * Some CPUs need to bypass caches to allow direct memory
155 * accesses, which is required for hardware virtualization.
156 */
157 bool bypassCaches() const {
158 return memoryMode == Enums::atomic_noncaching;
159 }
160 /** @} */
161
162 /** @{ */
163 /**
164 * Get the memory mode of the system.
165 *
166 * \warn This should only be used by the Python world. The C++
167 * world should use one of the query functions above
168 * (isAtomicMode(), isTimingMode(), bypassCaches()).
169 */
170 Enums::MemoryMode getMemoryMode() const { return memoryMode; }
171
172 /**
173 * Change the memory mode of the system.
174 *
175 * \warn This should only be called by the Python!
176 *
177 * @param mode Mode to change to (atomic/timing/...)
178 */
179 void setMemoryMode(Enums::MemoryMode mode);
180 /** @} */
181
182 /**
183 * Get the cache line size of the system.
184 */
185 unsigned int cacheLineSize() const { return _cacheLineSize; }
186
187#if THE_ISA != NULL_ISA
188 PCEventQueue pcEventQueue;
189#endif
190
191 std::vector<ThreadContext *> threadContexts;
192 int _numContexts;
193
194 ThreadContext *getThreadContext(ThreadID tid)
195 {
196 return threadContexts[tid];
197 }
198
199 int numContexts()
200 {
201 assert(_numContexts == (int)threadContexts.size());
202 return _numContexts;
203 }
204
205 /** Return number of running (non-halted) thread contexts in
206 * system. These threads could be Active or Suspended. */
207 int numRunningContexts();
208
209 Addr pagePtr;
210
211 uint64_t init_param;
212
213 /** Port to physical memory used for writing object files into ram at
214 * boot.*/
215 PortProxy physProxy;
216
217 /** kernel symbol table */
218 SymbolTable *kernelSymtab;
219
220 /** Object pointer for the kernel code */
221 ObjectFile *kernel;
222
223 /** Begining of kernel code */
224 Addr kernelStart;
225
226 /** End of kernel code */
227 Addr kernelEnd;
228
229 /** Entry point in the kernel to start at */
230 Addr kernelEntry;
231
232 /** Mask that should be anded for binary/symbol loading.
233 * This allows one two different OS requirements for the same ISA to be
234 * handled. Some OSes are compiled for a virtual address and need to be
235 * loaded into physical memory that starts at address 0, while other
236 * bare metal tools generate images that start at address 0.
237 */
238 Addr loadAddrMask;
239
|
| 240 /** Offset that should be used for binary/symbol loading.
241 * This further allows more flexibily than the loadAddrMask allows alone in
242 * loading kernels and similar. The loadAddrOffset is applied after the
243 * loadAddrMask.
244 */
245 Addr loadAddrOffset;
246
|
240 protected:
241 uint64_t nextPID;
242
243 public:
244 uint64_t allocatePID()
245 {
246 return nextPID++;
247 }
248
249 /** Get a pointer to access the physical memory of the system */
250 PhysicalMemory& getPhysMem() { return physmem; }
251
252 /** Amount of physical memory that is still free */
253 Addr freeMemSize() const;
254
255 /** Amount of physical memory that exists */
256 Addr memSize() const;
257
258 /**
259 * Check if a physical address is within a range of a memory that
260 * is part of the global address map.
261 *
262 * @param addr A physical address
263 * @return Whether the address corresponds to a memory
264 */
265 bool isMemAddr(Addr addr) const;
266
267 protected:
268
269 PhysicalMemory physmem;
270
271 Enums::MemoryMode memoryMode;
272
273 const unsigned int _cacheLineSize;
274
275 uint64_t workItemsBegin;
276 uint64_t workItemsEnd;
277 uint32_t numWorkIds;
278 std::vector<bool> activeCpus;
279
280 /** This array is a per-sytem list of all devices capable of issuing a
281 * memory system request and an associated string for each master id.
282 * It's used to uniquely id any master in the system by name for things
283 * like cache statistics.
284 */
285 std::vector<std::string> masterIds;
286
287 public:
288
289 /** Request an id used to create a request object in the system. All objects
290 * that intend to issues requests into the memory system must request an id
291 * in the init() phase of startup. All master ids must be fixed by the
292 * regStats() phase that immediately preceeds it. This allows objects in the
293 * memory system to understand how many masters may exist and
294 * appropriately name the bins of their per-master stats before the stats
295 * are finalized
296 */
297 MasterID getMasterId(std::string req_name);
298
299 /** Get the name of an object for a given request id.
300 */
301 std::string getMasterName(MasterID master_id);
302
303 /** Get the number of masters registered in the system */
304 MasterID maxMasters()
305 {
306 return masterIds.size();
307 }
308
309 virtual void regStats();
310 /**
311 * Called by pseudo_inst to track the number of work items started by this
312 * system.
313 */
314 uint64_t
315 incWorkItemsBegin()
316 {
317 return ++workItemsBegin;
318 }
319
320 /**
321 * Called by pseudo_inst to track the number of work items completed by
322 * this system.
323 */
| 247 protected:
248 uint64_t nextPID;
249
250 public:
251 uint64_t allocatePID()
252 {
253 return nextPID++;
254 }
255
256 /** Get a pointer to access the physical memory of the system */
257 PhysicalMemory& getPhysMem() { return physmem; }
258
259 /** Amount of physical memory that is still free */
260 Addr freeMemSize() const;
261
262 /** Amount of physical memory that exists */
263 Addr memSize() const;
264
265 /**
266 * Check if a physical address is within a range of a memory that
267 * is part of the global address map.
268 *
269 * @param addr A physical address
270 * @return Whether the address corresponds to a memory
271 */
272 bool isMemAddr(Addr addr) const;
273
274 protected:
275
276 PhysicalMemory physmem;
277
278 Enums::MemoryMode memoryMode;
279
280 const unsigned int _cacheLineSize;
281
282 uint64_t workItemsBegin;
283 uint64_t workItemsEnd;
284 uint32_t numWorkIds;
285 std::vector<bool> activeCpus;
286
287 /** This array is a per-sytem list of all devices capable of issuing a
288 * memory system request and an associated string for each master id.
289 * It's used to uniquely id any master in the system by name for things
290 * like cache statistics.
291 */
292 std::vector<std::string> masterIds;
293
294 public:
295
296 /** Request an id used to create a request object in the system. All objects
297 * that intend to issues requests into the memory system must request an id
298 * in the init() phase of startup. All master ids must be fixed by the
299 * regStats() phase that immediately preceeds it. This allows objects in the
300 * memory system to understand how many masters may exist and
301 * appropriately name the bins of their per-master stats before the stats
302 * are finalized
303 */
304 MasterID getMasterId(std::string req_name);
305
306 /** Get the name of an object for a given request id.
307 */
308 std::string getMasterName(MasterID master_id);
309
310 /** Get the number of masters registered in the system */
311 MasterID maxMasters()
312 {
313 return masterIds.size();
314 }
315
316 virtual void regStats();
317 /**
318 * Called by pseudo_inst to track the number of work items started by this
319 * system.
320 */
321 uint64_t
322 incWorkItemsBegin()
323 {
324 return ++workItemsBegin;
325 }
326
327 /**
328 * Called by pseudo_inst to track the number of work items completed by
329 * this system.
330 */
|
324 uint64_t
| 331 uint64_t
|
325 incWorkItemsEnd()
326 {
327 return ++workItemsEnd;
328 }
329
330 /**
331 * Called by pseudo_inst to mark the cpus actively executing work items.
332 * Returns the total number of cpus that have executed work item begin or
333 * ends.
334 */
| 332 incWorkItemsEnd()
333 {
334 return ++workItemsEnd;
335 }
336
337 /**
338 * Called by pseudo_inst to mark the cpus actively executing work items.
339 * Returns the total number of cpus that have executed work item begin or
340 * ends.
341 */
|
335 int
| 342 int
|
336 markWorkItem(int index)
337 {
338 int count = 0;
339 assert(index < activeCpus.size());
340 activeCpus[index] = true;
| 343 markWorkItem(int index)
344 {
345 int count = 0;
346 assert(index < activeCpus.size());
347 activeCpus[index] = true;
|
341 for (std::vector<bool>::iterator i = activeCpus.begin();
| 348 for (std::vector::iterator i = activeCpus.begin();
|
342 i < activeCpus.end(); i++) {
343 if (*i) count++;
344 }
345 return count;
346 }
347
348 inline void workItemBegin(uint32_t tid, uint32_t workid)
349 {
350 std::pair<uint32_t,uint32_t> p(tid, workid);
351 lastWorkItemStarted[p] = curTick();
352 }
353
354 void workItemEnd(uint32_t tid, uint32_t workid);
355
356 /**
357 * Fix up an address used to match PCs for hooking simulator
358 * events on to target function executions. See comment in
359 * system.cc for details.
360 */
361 virtual Addr fixFuncEventAddr(Addr addr)
362 {
363 panic("Base fixFuncEventAddr not implemented.\n");
364 }
365
366 /** @{ */
367 /**
368 * Add a function-based event to the given function, to be looked
369 * up in the specified symbol table.
370 *
371 * The ...OrPanic flavor of the method causes the simulator to
372 * panic if the symbol can't be found.
373 *
374 * @param symtab Symbol table to use for look up.
375 * @param lbl Function to hook the event to.
376 * @param desc Description to be passed to the event.
377 * @param args Arguments to be forwarded to the event constructor.
378 */
379 template <class T, typename... Args>
380 T *addFuncEvent(const SymbolTable *symtab, const char *lbl,
381 const std::string &desc, Args... args)
382 {
383 Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning
384
385#if THE_ISA != NULL_ISA
386 if (symtab->findAddress(lbl, addr)) {
387 T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr),
388 std::forward<Args>(args)...);
389 return ev;
390 }
391#endif
392
393 return NULL;
394 }
395
396 template <class T>
397 T *addFuncEvent(const SymbolTable *symtab, const char *lbl)
398 {
399 return addFuncEvent<T>(symtab, lbl, lbl);
400 }
401
402 template <class T, typename... Args>
403 T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl,
404 Args... args)
405 {
406 T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...));
407 if (!e)
408 panic("Failed to find symbol '%s'", lbl);
409 return e;
410 }
411 /** @} */
412
413 /** @{ */
414 /**
415 * Add a function-based event to a kernel symbol.
416 *
417 * These functions work like their addFuncEvent() and
418 * addFuncEventOrPanic() counterparts. The only difference is that
419 * they automatically use the kernel symbol table. All arguments
420 * are forwarded to the underlying method.
421 *
422 * @see addFuncEvent()
423 * @see addFuncEventOrPanic()
424 *
425 * @param lbl Function to hook the event to.
426 * @param args Arguments to be passed to addFuncEvent
427 */
428 template <class T, typename... Args>
429 T *addKernelFuncEvent(const char *lbl, Args... args)
430 {
431 return addFuncEvent<T>(kernelSymtab, lbl,
432 std::forward<Args>(args)...);
433 }
434
435 template <class T, typename... Args>
436 T *addKernelFuncEventOrPanic(const char *lbl, Args... args)
437 {
438 T *e(addFuncEvent<T>(kernelSymtab, lbl,
439 std::forward<Args>(args)...));
440 if (!e)
441 panic("Failed to find kernel symbol '%s'", lbl);
442 return e;
443 }
444 /** @} */
445
446 public:
447 std::vector<BaseRemoteGDB *> remoteGDB;
448 std::vector<GDBListener *> gdbListen;
449 bool breakpoint();
450
451 public:
452 typedef SystemParams Params;
453
454 protected:
455 Params *_params;
456
457 public:
458 System(Params *p);
459 ~System();
460
461 void initState();
462
463 const Params *params() const { return (const Params *)_params; }
464
465 public:
466
467 /**
468 * Returns the addess the kernel starts at.
469 * @return address the kernel starts at
470 */
471 Addr getKernelStart() const { return kernelStart; }
472
473 /**
474 * Returns the addess the kernel ends at.
475 * @return address the kernel ends at
476 */
477 Addr getKernelEnd() const { return kernelEnd; }
478
479 /**
480 * Returns the addess the entry point to the kernel code.
481 * @return entry point of the kernel code
482 */
483 Addr getKernelEntry() const { return kernelEntry; }
484
485 /// Allocate npages contiguous unused physical pages
486 /// @return Starting address of first page
487 Addr allocPhysPages(int npages);
488
489 int registerThreadContext(ThreadContext *tc, int assigned=-1);
490 void replaceThreadContext(ThreadContext *tc, int context_id);
491
492 void serialize(std::ostream &os);
493 void unserialize(Checkpoint *cp, const std::string §ion);
494
495 unsigned int drain(DrainManager *dm);
496 void drainResume();
497
498 public:
499 Counter totalNumInsts;
500 EventQueue instEventQueue;
501 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted;
502 std::map<uint32_t, Stats::Histogram*> workItemStats;
503
504 ////////////////////////////////////////////
505 //
506 // STATIC GLOBAL SYSTEM LIST
507 //
508 ////////////////////////////////////////////
509
510 static std::vector<System *> systemList;
511 static int numSystemsRunning;
512
513 static void printSystems();
514
515 // For futex system call
516 std::map<uint64_t, std::list<ThreadContext *> * > futexMap;
517
518 protected:
519
520 /**
521 * If needed, serialize additional symbol table entries for a
522 * specific subclass of this sytem. Currently this is used by
523 * Alpha and MIPS.
524 *
525 * @param os stream to serialize to
526 */
527 virtual void serializeSymtab(std::ostream &os) {}
528
529 /**
530 * If needed, unserialize additional symbol table entries for a
531 * specific subclass of this system.
532 *
533 * @param cp checkpoint to unserialize from
534 * @param section relevant section in the checkpoint
535 */
536 virtual void unserializeSymtab(Checkpoint *cp,
537 const std::string §ion) {}
538
539};
540
541void printSystems();
542
543#endif // __SYSTEM_HH__
| 349 i < activeCpus.end(); i++) {
350 if (*i) count++;
351 }
352 return count;
353 }
354
355 inline void workItemBegin(uint32_t tid, uint32_t workid)
356 {
357 std::pair<uint32_t,uint32_t> p(tid, workid);
358 lastWorkItemStarted[p] = curTick();
359 }
360
361 void workItemEnd(uint32_t tid, uint32_t workid);
362
363 /**
364 * Fix up an address used to match PCs for hooking simulator
365 * events on to target function executions. See comment in
366 * system.cc for details.
367 */
368 virtual Addr fixFuncEventAddr(Addr addr)
369 {
370 panic("Base fixFuncEventAddr not implemented.\n");
371 }
372
373 /** @{ */
374 /**
375 * Add a function-based event to the given function, to be looked
376 * up in the specified symbol table.
377 *
378 * The ...OrPanic flavor of the method causes the simulator to
379 * panic if the symbol can't be found.
380 *
381 * @param symtab Symbol table to use for look up.
382 * @param lbl Function to hook the event to.
383 * @param desc Description to be passed to the event.
384 * @param args Arguments to be forwarded to the event constructor.
385 */
386 template <class T, typename... Args>
387 T *addFuncEvent(const SymbolTable *symtab, const char *lbl,
388 const std::string &desc, Args... args)
389 {
390 Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning
391
392#if THE_ISA != NULL_ISA
393 if (symtab->findAddress(lbl, addr)) {
394 T *ev = new T(&pcEventQueue, desc, fixFuncEventAddr(addr),
395 std::forward<Args>(args)...);
396 return ev;
397 }
398#endif
399
400 return NULL;
401 }
402
403 template <class T>
404 T *addFuncEvent(const SymbolTable *symtab, const char *lbl)
405 {
406 return addFuncEvent<T>(symtab, lbl, lbl);
407 }
408
409 template <class T, typename... Args>
410 T *addFuncEventOrPanic(const SymbolTable *symtab, const char *lbl,
411 Args... args)
412 {
413 T *e(addFuncEvent<T>(symtab, lbl, std::forward<Args>(args)...));
414 if (!e)
415 panic("Failed to find symbol '%s'", lbl);
416 return e;
417 }
418 /** @} */
419
420 /** @{ */
421 /**
422 * Add a function-based event to a kernel symbol.
423 *
424 * These functions work like their addFuncEvent() and
425 * addFuncEventOrPanic() counterparts. The only difference is that
426 * they automatically use the kernel symbol table. All arguments
427 * are forwarded to the underlying method.
428 *
429 * @see addFuncEvent()
430 * @see addFuncEventOrPanic()
431 *
432 * @param lbl Function to hook the event to.
433 * @param args Arguments to be passed to addFuncEvent
434 */
435 template <class T, typename... Args>
436 T *addKernelFuncEvent(const char *lbl, Args... args)
437 {
438 return addFuncEvent<T>(kernelSymtab, lbl,
439 std::forward<Args>(args)...);
440 }
441
442 template <class T, typename... Args>
443 T *addKernelFuncEventOrPanic(const char *lbl, Args... args)
444 {
445 T *e(addFuncEvent<T>(kernelSymtab, lbl,
446 std::forward<Args>(args)...));
447 if (!e)
448 panic("Failed to find kernel symbol '%s'", lbl);
449 return e;
450 }
451 /** @} */
452
453 public:
454 std::vector<BaseRemoteGDB *> remoteGDB;
455 std::vector<GDBListener *> gdbListen;
456 bool breakpoint();
457
458 public:
459 typedef SystemParams Params;
460
461 protected:
462 Params *_params;
463
464 public:
465 System(Params *p);
466 ~System();
467
468 void initState();
469
470 const Params *params() const { return (const Params *)_params; }
471
472 public:
473
474 /**
475 * Returns the addess the kernel starts at.
476 * @return address the kernel starts at
477 */
478 Addr getKernelStart() const { return kernelStart; }
479
480 /**
481 * Returns the addess the kernel ends at.
482 * @return address the kernel ends at
483 */
484 Addr getKernelEnd() const { return kernelEnd; }
485
486 /**
487 * Returns the addess the entry point to the kernel code.
488 * @return entry point of the kernel code
489 */
490 Addr getKernelEntry() const { return kernelEntry; }
491
492 /// Allocate npages contiguous unused physical pages
493 /// @return Starting address of first page
494 Addr allocPhysPages(int npages);
495
496 int registerThreadContext(ThreadContext *tc, int assigned=-1);
497 void replaceThreadContext(ThreadContext *tc, int context_id);
498
499 void serialize(std::ostream &os);
500 void unserialize(Checkpoint *cp, const std::string §ion);
501
502 unsigned int drain(DrainManager *dm);
503 void drainResume();
504
505 public:
506 Counter totalNumInsts;
507 EventQueue instEventQueue;
508 std::map<std::pair<uint32_t,uint32_t>, Tick> lastWorkItemStarted;
509 std::map<uint32_t, Stats::Histogram*> workItemStats;
510
511 ////////////////////////////////////////////
512 //
513 // STATIC GLOBAL SYSTEM LIST
514 //
515 ////////////////////////////////////////////
516
517 static std::vector<System *> systemList;
518 static int numSystemsRunning;
519
520 static void printSystems();
521
522 // For futex system call
523 std::map<uint64_t, std::list<ThreadContext *> * > futexMap;
524
525 protected:
526
527 /**
528 * If needed, serialize additional symbol table entries for a
529 * specific subclass of this sytem. Currently this is used by
530 * Alpha and MIPS.
531 *
532 * @param os stream to serialize to
533 */
534 virtual void serializeSymtab(std::ostream &os) {}
535
536 /**
537 * If needed, unserialize additional symbol table entries for a
538 * specific subclass of this system.
539 *
540 * @param cp checkpoint to unserialize from
541 * @param section relevant section in the checkpoint
542 */
543 virtual void unserializeSymtab(Checkpoint *cp,
544 const std::string §ion) {}
545
546};
547
548void printSystems();
549
550#endif // __SYSTEM_HH__
|