1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31// This file will contain default statistics for the simulator that
32// don't really belong to a specific simulator object
33
34#include <fstream>
35#include <iostream>
36#include <list>
37
38#include "base/callback.hh"
39#include "base/hostinfo.hh"
40#include "base/statistics.hh"
41#include "base/time.hh"
42
43#include "config/the_isa.hh"
44#if THE_ISA == NO_ISA
45#include "arch/noisa/cpu_dummy.hh"
46#else
47#include "cpu/base.hh"
48#endif
49
50#include "sim/eventq.hh"
51#include "sim/stat_control.hh"
52
53using namespace std;
54
55Stats::Formula simSeconds;
56Stats::Value simTicks;
57Stats::Value simFreq;
58
59namespace Stats {
60
61Time statTime(true);
62Tick startTick;
63
64struct SimTicksReset : public Callback
65{
66 void process()
67 {
68 statTime.set();
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31// This file will contain default statistics for the simulator that
32// don't really belong to a specific simulator object
33
34#include <fstream>
35#include <iostream>
36#include <list>
37
38#include "base/callback.hh"
39#include "base/hostinfo.hh"
40#include "base/statistics.hh"
41#include "base/time.hh"
42
43#include "config/the_isa.hh"
44#if THE_ISA == NO_ISA
45#include "arch/noisa/cpu_dummy.hh"
46#else
47#include "cpu/base.hh"
48#endif
49
50#include "sim/eventq.hh"
51#include "sim/stat_control.hh"
52
53using namespace std;
54
55Stats::Formula simSeconds;
56Stats::Value simTicks;
57Stats::Value simFreq;
58
59namespace Stats {
60
61Time statTime(true);
62Tick startTick;
63
64struct SimTicksReset : public Callback
65{
66 void process()
67 {
68 statTime.set();
|
69 startTick = curTick;
| 69 startTick = curTick();
|
70 }
71};
72
73double
74statElapsedTime()
75{
76 Time now(true);
77 Time elapsed = now - statTime;
78 return elapsed();
79}
80
81Tick
82statElapsedTicks()
83{
| 70 }
71};
72
73double
74statElapsedTime()
75{
76 Time now(true);
77 Time elapsed = now - statTime;
78 return elapsed();
79}
80
81Tick
82statElapsedTicks()
83{
|
84 return curTick - startTick;
| 84 return curTick() - startTick;
|
85}
86
87SimTicksReset simTicksReset;
88
89struct Global
90{
91 Stats::Formula hostInstRate;
92 Stats::Formula hostTickRate;
93 Stats::Value hostMemory;
94 Stats::Value hostSeconds;
95
96 Stats::Value simInsts;
97
98 Global();
99};
100
101Global::Global()
102{
103 simInsts
104 .functor(BaseCPU::numSimulatedInstructions)
105 .name("sim_insts")
106 .desc("Number of instructions simulated")
107 .precision(0)
108 .prereq(simInsts)
109 ;
110
111 simSeconds
112 .name("sim_seconds")
113 .desc("Number of seconds simulated")
114 ;
115
116 simFreq
117 .scalar(SimClock::Frequency)
118 .name("sim_freq")
119 .desc("Frequency of simulated ticks")
120 ;
121
122 simTicks
123 .functor(statElapsedTicks)
124 .name("sim_ticks")
125 .desc("Number of ticks simulated")
126 ;
127
128 hostInstRate
129 .name("host_inst_rate")
130 .desc("Simulator instruction rate (inst/s)")
131 .precision(0)
132 .prereq(simInsts)
133 ;
134
135 hostMemory
136 .functor(memUsage)
137 .name("host_mem_usage")
138 .desc("Number of bytes of host memory used")
139 .prereq(hostMemory)
140 ;
141
142 hostSeconds
143 .functor(statElapsedTime)
144 .name("host_seconds")
145 .desc("Real time elapsed on the host")
146 .precision(2)
147 ;
148
149 hostTickRate
150 .name("host_tick_rate")
151 .desc("Simulator tick rate (ticks/s)")
152 .precision(0)
153 ;
154
155 simSeconds = simTicks / simFreq;
156 hostInstRate = simInsts / hostSeconds;
157 hostTickRate = simTicks / hostSeconds;
158
159 registerResetCallback(&simTicksReset);
160}
161
162void
163initSimStats()
164{
165 static Global global;
166}
167
168class StatEvent : public Event
169{
170 private:
171 bool dump;
172 bool reset;
173 Tick repeat;
174
175 public:
176 StatEvent(bool _dump, bool _reset, Tick _repeat)
177 : Event(Stat_Event_Pri), dump(_dump), reset(_reset), repeat(_repeat)
178 {
179 setFlags(AutoDelete);
180 }
181
182 virtual void
183 process()
184 {
185 if (dump)
186 Stats::dump();
187
188 if (reset)
189 Stats::reset();
190
191 if (repeat) {
| 85}
86
87SimTicksReset simTicksReset;
88
89struct Global
90{
91 Stats::Formula hostInstRate;
92 Stats::Formula hostTickRate;
93 Stats::Value hostMemory;
94 Stats::Value hostSeconds;
95
96 Stats::Value simInsts;
97
98 Global();
99};
100
101Global::Global()
102{
103 simInsts
104 .functor(BaseCPU::numSimulatedInstructions)
105 .name("sim_insts")
106 .desc("Number of instructions simulated")
107 .precision(0)
108 .prereq(simInsts)
109 ;
110
111 simSeconds
112 .name("sim_seconds")
113 .desc("Number of seconds simulated")
114 ;
115
116 simFreq
117 .scalar(SimClock::Frequency)
118 .name("sim_freq")
119 .desc("Frequency of simulated ticks")
120 ;
121
122 simTicks
123 .functor(statElapsedTicks)
124 .name("sim_ticks")
125 .desc("Number of ticks simulated")
126 ;
127
128 hostInstRate
129 .name("host_inst_rate")
130 .desc("Simulator instruction rate (inst/s)")
131 .precision(0)
132 .prereq(simInsts)
133 ;
134
135 hostMemory
136 .functor(memUsage)
137 .name("host_mem_usage")
138 .desc("Number of bytes of host memory used")
139 .prereq(hostMemory)
140 ;
141
142 hostSeconds
143 .functor(statElapsedTime)
144 .name("host_seconds")
145 .desc("Real time elapsed on the host")
146 .precision(2)
147 ;
148
149 hostTickRate
150 .name("host_tick_rate")
151 .desc("Simulator tick rate (ticks/s)")
152 .precision(0)
153 ;
154
155 simSeconds = simTicks / simFreq;
156 hostInstRate = simInsts / hostSeconds;
157 hostTickRate = simTicks / hostSeconds;
158
159 registerResetCallback(&simTicksReset);
160}
161
162void
163initSimStats()
164{
165 static Global global;
166}
167
168class StatEvent : public Event
169{
170 private:
171 bool dump;
172 bool reset;
173 Tick repeat;
174
175 public:
176 StatEvent(bool _dump, bool _reset, Tick _repeat)
177 : Event(Stat_Event_Pri), dump(_dump), reset(_reset), repeat(_repeat)
178 {
179 setFlags(AutoDelete);
180 }
181
182 virtual void
183 process()
184 {
185 if (dump)
186 Stats::dump();
187
188 if (reset)
189 Stats::reset();
190
191 if (repeat) {
|
192 Stats::schedStatEvent(dump, reset, curTick + repeat, repeat);
| 192 Stats::schedStatEvent(dump, reset, curTick() + repeat, repeat);
|
193 }
194 }
195};
196
197void
198schedStatEvent(bool dump, bool reset, Tick when, Tick repeat)
199{
200 Event *event = new StatEvent(dump, reset, repeat);
201 mainEventQueue.schedule(event, when);
202}
203
204} // namespace Stats
| 193 }
194 }
195};
196
197void
198schedStatEvent(bool dump, bool reset, Tick when, Tick repeat)
199{
200 Event *event = new StatEvent(dump, reset, repeat);
201 mainEventQueue.schedule(event, when);
202}
203
204} // namespace Stats
|