1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31// This file will contain default statistics for the simulator that
32// don't really belong to a specific simulator object
33
34#include <fstream>
35#include <iostream>
36#include <list>
37
38#include "base/callback.hh"
39#include "base/hostinfo.hh"
40#include "base/statistics.hh"
41#include "base/time.hh"
42#include "cpu/base.hh"
43#include "sim/eventq.hh"
44
45using namespace std;
46
47Stats::Formula hostInstRate;
48Stats::Formula hostTickRate;
49Stats::Value hostMemory;
50Stats::Value hostSeconds;
51
52Stats::Value simTicks;
53Stats::Value simInsts;
54Stats::Value simFreq;
55Stats::Formula simSeconds;
56
57namespace Stats {
58
59Time statTime(true);
60Tick startTick;
61
62struct SimTicksReset : public Callback
63{
64 void process()
65 {
66 statTime.set();
67 startTick = curTick;
68 }
69};
70
71double
72statElapsedTime()
73{
74 Time now(true);
75 Time elapsed = now - statTime;
76 return elapsed();
77}
78
79Tick
80statElapsedTicks()
81{
82 return curTick - startTick;
83}
84
85SimTicksReset simTicksReset;
86
87void
88initSimStats()
89{
90 simInsts
91 .functor(BaseCPU::numSimulatedInstructions)
92 .name("sim_insts")
93 .desc("Number of instructions simulated")
94 .precision(0)
95 .prereq(simInsts)
96 ;
97
98 simSeconds
99 .name("sim_seconds")
100 .desc("Number of seconds simulated")
101 ;
102
103 simFreq
104 .scalar(Clock::Frequency)
105 .name("sim_freq")
106 .desc("Frequency of simulated ticks")
107 ;
108
109 simTicks
110 .functor(statElapsedTicks)
111 .name("sim_ticks")
112 .desc("Number of ticks simulated")
113 ;
114
115 hostInstRate
116 .name("host_inst_rate")
117 .desc("Simulator instruction rate (inst/s)")
118 .precision(0)
119 .prereq(simInsts)
120 ;
121
122 hostMemory
123 .functor(memUsage)
124 .name("host_mem_usage")
125 .desc("Number of bytes of host memory used")
126 .prereq(hostMemory)
127 ;
128
129 hostSeconds
130 .functor(statElapsedTime)
131 .name("host_seconds")
132 .desc("Real time elapsed on the host")
133 .precision(2)
134 ;
135
136 hostTickRate
137 .name("host_tick_rate")
138 .desc("Simulator tick rate (ticks/s)")
139 .precision(0)
140 ;
141
142 simSeconds = simTicks / simFreq;
143 hostInstRate = simInsts / hostSeconds;
144 hostTickRate = simTicks / hostSeconds;
145
146 registerResetCallback(&simTicksReset);
147}
148
149class _StatEvent : public Event
150{
151 private:
152 bool dump;
153 bool reset;
154 Tick repeat;
155
156 public:
| 1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31// This file will contain default statistics for the simulator that
32// don't really belong to a specific simulator object
33
34#include <fstream>
35#include <iostream>
36#include <list>
37
38#include "base/callback.hh"
39#include "base/hostinfo.hh"
40#include "base/statistics.hh"
41#include "base/time.hh"
42#include "cpu/base.hh"
43#include "sim/eventq.hh"
44
45using namespace std;
46
47Stats::Formula hostInstRate;
48Stats::Formula hostTickRate;
49Stats::Value hostMemory;
50Stats::Value hostSeconds;
51
52Stats::Value simTicks;
53Stats::Value simInsts;
54Stats::Value simFreq;
55Stats::Formula simSeconds;
56
57namespace Stats {
58
59Time statTime(true);
60Tick startTick;
61
62struct SimTicksReset : public Callback
63{
64 void process()
65 {
66 statTime.set();
67 startTick = curTick;
68 }
69};
70
71double
72statElapsedTime()
73{
74 Time now(true);
75 Time elapsed = now - statTime;
76 return elapsed();
77}
78
79Tick
80statElapsedTicks()
81{
82 return curTick - startTick;
83}
84
85SimTicksReset simTicksReset;
86
87void
88initSimStats()
89{
90 simInsts
91 .functor(BaseCPU::numSimulatedInstructions)
92 .name("sim_insts")
93 .desc("Number of instructions simulated")
94 .precision(0)
95 .prereq(simInsts)
96 ;
97
98 simSeconds
99 .name("sim_seconds")
100 .desc("Number of seconds simulated")
101 ;
102
103 simFreq
104 .scalar(Clock::Frequency)
105 .name("sim_freq")
106 .desc("Frequency of simulated ticks")
107 ;
108
109 simTicks
110 .functor(statElapsedTicks)
111 .name("sim_ticks")
112 .desc("Number of ticks simulated")
113 ;
114
115 hostInstRate
116 .name("host_inst_rate")
117 .desc("Simulator instruction rate (inst/s)")
118 .precision(0)
119 .prereq(simInsts)
120 ;
121
122 hostMemory
123 .functor(memUsage)
124 .name("host_mem_usage")
125 .desc("Number of bytes of host memory used")
126 .prereq(hostMemory)
127 ;
128
129 hostSeconds
130 .functor(statElapsedTime)
131 .name("host_seconds")
132 .desc("Real time elapsed on the host")
133 .precision(2)
134 ;
135
136 hostTickRate
137 .name("host_tick_rate")
138 .desc("Simulator tick rate (ticks/s)")
139 .precision(0)
140 ;
141
142 simSeconds = simTicks / simFreq;
143 hostInstRate = simInsts / hostSeconds;
144 hostTickRate = simTicks / hostSeconds;
145
146 registerResetCallback(&simTicksReset);
147}
148
149class _StatEvent : public Event
150{
151 private:
152 bool dump;
153 bool reset;
154 Tick repeat;
155
156 public:
|
157 _StatEvent(bool _dump, bool _reset, Tick _when, Tick _repeat)
158 : Event(&mainEventQueue, Stat_Event_Pri), dump(_dump), reset(_reset),
159 repeat(_repeat)
| 157 _StatEvent(bool _dump, bool _reset, Tick _repeat)
158 : Event(Stat_Event_Pri), dump(_dump), reset(_reset), repeat(_repeat)
|
160 {
161 setFlags(AutoDelete);
| 159 {
160 setFlags(AutoDelete);
|
162 schedule(_when);
| |
163 }
164
165 virtual void
166 process()
167 {
168 if (dump)
169 Stats::dump();
170
171 if (reset)
172 Stats::reset();
173
| 161 }
162
163 virtual void
164 process()
165 {
166 if (dump)
167 Stats::dump();
168
169 if (reset)
170 Stats::reset();
171
|
174 if (repeat)
175 new _StatEvent(dump, reset, curTick + repeat, repeat);
| 172 if (repeat) {
173 Event *event = new _StatEvent(dump, reset, repeat);
174 mainEventQueue.schedule(event, curTick + repeat);
175 }
|
176 }
177};
178
179void
180StatEvent(bool dump, bool reset, Tick when, Tick repeat)
181{
| 176 }
177};
178
179void
180StatEvent(bool dump, bool reset, Tick when, Tick repeat)
181{
|
182 new _StatEvent(dump, reset, when, repeat);
| 182 Event *event = new _StatEvent(dump, reset, repeat);
183 mainEventQueue.schedule(event, when);
|
183}
184
185/* namespace Stats */ }
| 184}
185
186/* namespace Stats */ }
|