sim_object.hh (11067:5379f099e488) sim_object.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 */
44
45/* @file
46 * User Console Definitions
47 */
48
49#ifndef __SIM_OBJECT_HH__
50#define __SIM_OBJECT_HH__
51
52#include <iostream>
53#include <list>
54#include <map>
55#include <string>
56#include <vector>
57
58#include "enums/MemoryMode.hh"
59#include "params/SimObject.hh"
60#include "sim/drain.hh"
61#include "sim/eventq_impl.hh"
62#include "sim/serialize.hh"
63
64class BaseCPU;
65class Event;
66class ProbeManager;
67/**
68 * Abstract superclass for simulation objects. Represents things that
69 * correspond to physical components and can be specified via the
70 * config file (CPUs, caches, etc.).
71 *
72 * SimObject initialization is controlled by the instantiate method in
73 * src/python/m5/simulate.py. There are slightly different
74 * initialization paths when starting the simulation afresh and when
75 * loading from a checkpoint. After instantiation and connecting
76 * ports, simulate.py initializes the object using the following call
77 * sequence:
78 *
79 * <ol>
80 * <li>SimObject::init()
81 * <li>SimObject::regStats()
82 * <li><ul>
83 * <li>SimObject::initState() if starting afresh.
84 * <li>SimObject::loadState() if restoring from a checkpoint.
85 * </ul>
86 * <li>SimObject::resetStats()
87 * <li>SimObject::startup()
88 * <li>Drainable::drainResume() if resuming from a checkpoint.
89 * </ol>
90 *
91 * @note Whenever a method is called on all objects in the simulator's
92 * object tree (e.g., init(), startup(), or loadState()), a pre-order
93 * depth-first traversal is performed (see descendants() in
94 * SimObject.py). This has the effect of calling the method on the
95 * parent node <i>before</i> its children.
96 */
97class SimObject : public EventManager, public Serializable, public Drainable
98{
99 private:
100 typedef std::vector<SimObject *> SimObjectList;
101
102 /** List of all instantiated simulation objects. */
103 static SimObjectList simObjectList;
104
105 /** Manager coordinates hooking up probe points with listeners. */
106 ProbeManager *probeManager;
107
108 protected:
109 /** Cached copy of the object parameters. */
110 const SimObjectParams *_params;
111
112 public:
113 typedef SimObjectParams Params;
114 const Params *params() const { return _params; }
115 SimObject(const Params *_params);
116 virtual ~SimObject();
117
118 public:
119
120 virtual const std::string name() const { return params()->name; }
121
122 /**
123 * init() is called after all C++ SimObjects have been created and
124 * all ports are connected. Initializations that are independent
125 * of unserialization but rely on a fully instantiated and
126 * connected SimObject graph should be done here.
127 */
128 virtual void init();
129
130 /**
131 * loadState() is called on each SimObject when restoring from a
132 * checkpoint. The default implementation simply calls
133 * unserialize() if there is a corresponding section in the
134 * checkpoint. However, objects can override loadState() to get
135 * other behaviors, e.g., doing other programmed initializations
136 * after unserialize(), or complaining if no checkpoint section is
137 * found.
138 *
139 * @param cp Checkpoint to restore the state from.
140 */
141 virtual void loadState(CheckpointIn &cp);
142
143 /**
144 * initState() is called on each SimObject when *not* restoring
145 * from a checkpoint. This provides a hook for state
146 * initializations that are only required for a "cold start".
147 */
148 virtual void initState();
149
150 /**
151 * Register statistics for this object.
152 */
153 virtual void regStats();
154
155 /**
156 * Reset statistics associated with this object.
157 */
158 virtual void resetStats();
159
160 /**
161 * Register probe points for this object.
162 */
163 virtual void regProbePoints();
164
165 /**
166 * Register probe listeners for this object.
167 */
168 virtual void regProbeListeners();
169
170 /**
171 * Get the probe manager for this object.
172 */
173 ProbeManager *getProbeManager();
174
175 /**
176 * startup() is the final initialization call before simulation.
177 * All state is initialized (including unserialized state, if any,
178 * such as the curTick() value), so this is the appropriate place to
179 * schedule initial event(s) for objects that need them.
180 */
181 virtual void startup();
182
183 /**
184 * Provide a default implementation of the drain interface for
185 * objects that don't need draining.
186 */
1/*
2 * Copyright (c) 2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Steve Reinhardt
42 * Nathan Binkert
43 */
44
45/* @file
46 * User Console Definitions
47 */
48
49#ifndef __SIM_OBJECT_HH__
50#define __SIM_OBJECT_HH__
51
52#include <iostream>
53#include <list>
54#include <map>
55#include <string>
56#include <vector>
57
58#include "enums/MemoryMode.hh"
59#include "params/SimObject.hh"
60#include "sim/drain.hh"
61#include "sim/eventq_impl.hh"
62#include "sim/serialize.hh"
63
64class BaseCPU;
65class Event;
66class ProbeManager;
67/**
68 * Abstract superclass for simulation objects. Represents things that
69 * correspond to physical components and can be specified via the
70 * config file (CPUs, caches, etc.).
71 *
72 * SimObject initialization is controlled by the instantiate method in
73 * src/python/m5/simulate.py. There are slightly different
74 * initialization paths when starting the simulation afresh and when
75 * loading from a checkpoint. After instantiation and connecting
76 * ports, simulate.py initializes the object using the following call
77 * sequence:
78 *
79 * <ol>
80 * <li>SimObject::init()
81 * <li>SimObject::regStats()
82 * <li><ul>
83 * <li>SimObject::initState() if starting afresh.
84 * <li>SimObject::loadState() if restoring from a checkpoint.
85 * </ul>
86 * <li>SimObject::resetStats()
87 * <li>SimObject::startup()
88 * <li>Drainable::drainResume() if resuming from a checkpoint.
89 * </ol>
90 *
91 * @note Whenever a method is called on all objects in the simulator's
92 * object tree (e.g., init(), startup(), or loadState()), a pre-order
93 * depth-first traversal is performed (see descendants() in
94 * SimObject.py). This has the effect of calling the method on the
95 * parent node <i>before</i> its children.
96 */
97class SimObject : public EventManager, public Serializable, public Drainable
98{
99 private:
100 typedef std::vector<SimObject *> SimObjectList;
101
102 /** List of all instantiated simulation objects. */
103 static SimObjectList simObjectList;
104
105 /** Manager coordinates hooking up probe points with listeners. */
106 ProbeManager *probeManager;
107
108 protected:
109 /** Cached copy of the object parameters. */
110 const SimObjectParams *_params;
111
112 public:
113 typedef SimObjectParams Params;
114 const Params *params() const { return _params; }
115 SimObject(const Params *_params);
116 virtual ~SimObject();
117
118 public:
119
120 virtual const std::string name() const { return params()->name; }
121
122 /**
123 * init() is called after all C++ SimObjects have been created and
124 * all ports are connected. Initializations that are independent
125 * of unserialization but rely on a fully instantiated and
126 * connected SimObject graph should be done here.
127 */
128 virtual void init();
129
130 /**
131 * loadState() is called on each SimObject when restoring from a
132 * checkpoint. The default implementation simply calls
133 * unserialize() if there is a corresponding section in the
134 * checkpoint. However, objects can override loadState() to get
135 * other behaviors, e.g., doing other programmed initializations
136 * after unserialize(), or complaining if no checkpoint section is
137 * found.
138 *
139 * @param cp Checkpoint to restore the state from.
140 */
141 virtual void loadState(CheckpointIn &cp);
142
143 /**
144 * initState() is called on each SimObject when *not* restoring
145 * from a checkpoint. This provides a hook for state
146 * initializations that are only required for a "cold start".
147 */
148 virtual void initState();
149
150 /**
151 * Register statistics for this object.
152 */
153 virtual void regStats();
154
155 /**
156 * Reset statistics associated with this object.
157 */
158 virtual void resetStats();
159
160 /**
161 * Register probe points for this object.
162 */
163 virtual void regProbePoints();
164
165 /**
166 * Register probe listeners for this object.
167 */
168 virtual void regProbeListeners();
169
170 /**
171 * Get the probe manager for this object.
172 */
173 ProbeManager *getProbeManager();
174
175 /**
176 * startup() is the final initialization call before simulation.
177 * All state is initialized (including unserialized state, if any,
178 * such as the curTick() value), so this is the appropriate place to
179 * schedule initial event(s) for objects that need them.
180 */
181 virtual void startup();
182
183 /**
184 * Provide a default implementation of the drain interface for
185 * objects that don't need draining.
186 */
187 DrainState drain() M5_ATTR_OVERRIDE { return DrainState::Drained; }
187 DrainState drain() override { return DrainState::Drained; }
188
189 /**
190 * Write back dirty buffers to memory using functional writes.
191 *
192 * After returning, an object implementing this method should have
193 * written all its dirty data back to memory. This method is
194 * typically used to prepare a system with caches for
195 * checkpointing.
196 */
197 virtual void memWriteback() {};
198
199 /**
200 * Invalidate the contents of memory buffers.
201 *
202 * When the switching to hardware virtualized CPU models, we need
203 * to make sure that we don't have any cached state in the system
204 * that might become stale when we return. This method is used to
205 * flush all such state back to main memory.
206 *
207 * @warn This does <i>not</i> cause any dirty state to be written
208 * back to memory.
209 */
210 virtual void memInvalidate() {};
211
188
189 /**
190 * Write back dirty buffers to memory using functional writes.
191 *
192 * After returning, an object implementing this method should have
193 * written all its dirty data back to memory. This method is
194 * typically used to prepare a system with caches for
195 * checkpointing.
196 */
197 virtual void memWriteback() {};
198
199 /**
200 * Invalidate the contents of memory buffers.
201 *
202 * When the switching to hardware virtualized CPU models, we need
203 * to make sure that we don't have any cached state in the system
204 * that might become stale when we return. This method is used to
205 * flush all such state back to main memory.
206 *
207 * @warn This does <i>not</i> cause any dirty state to be written
208 * back to memory.
209 */
210 virtual void memInvalidate() {};
211
212 void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE {};
213 void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE {};
212 void serialize(CheckpointOut &cp) const override {};
213 void unserialize(CheckpointIn &cp) override {};
214
215 /**
216 * Serialize all SimObjects in the system.
217 */
218 static void serializeAll(CheckpointOut &cp);
219
220#ifdef DEBUG
221 public:
222 bool doDebugBreak;
223 static void debugObjectBreak(const std::string &objs);
224#endif
225
226 /**
227 * Find the SimObject with the given name and return a pointer to
228 * it. Primarily used for interactive debugging. Argument is
229 * char* rather than std::string to make it callable from gdb.
230 */
231 static SimObject *find(const char *name);
232};
233
234/**
235 * Base class to wrap object resolving functionality.
236 *
237 * This can be provided to the serialization framework to allow it to
238 * map object names onto C++ objects.
239 */
240class SimObjectResolver
241{
242 public:
243 virtual ~SimObjectResolver() { }
244
245 // Find a SimObject given a full path name
246 virtual SimObject *resolveSimObject(const std::string &name) = 0;
247};
248
249#ifdef DEBUG
250void debugObjectBreak(const char *objs);
251#endif
252
253#endif // __SIM_OBJECT_HH__
214
215 /**
216 * Serialize all SimObjects in the system.
217 */
218 static void serializeAll(CheckpointOut &cp);
219
220#ifdef DEBUG
221 public:
222 bool doDebugBreak;
223 static void debugObjectBreak(const std::string &objs);
224#endif
225
226 /**
227 * Find the SimObject with the given name and return a pointer to
228 * it. Primarily used for interactive debugging. Argument is
229 * char* rather than std::string to make it callable from gdb.
230 */
231 static SimObject *find(const char *name);
232};
233
234/**
235 * Base class to wrap object resolving functionality.
236 *
237 * This can be provided to the serialization framework to allow it to
238 * map object names onto C++ objects.
239 */
240class SimObjectResolver
241{
242 public:
243 virtual ~SimObjectResolver() { }
244
245 // Find a SimObject given a full path name
246 virtual SimObject *resolveSimObject(const std::string &name) = 0;
247};
248
249#ifdef DEBUG
250void debugObjectBreak(const char *objs);
251#endif
252
253#endif // __SIM_OBJECT_HH__