sim_object.cc (2802:babfc298ac86) sim_object.cc (2806:2e42ac0e7bd0)
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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68 : _params(p)
69{
70#ifdef DEBUG
71 doDebugBreak = false;
72#endif
73
74 doRecordEvent = !Stats::event_ignore.match(name());
75 simObjectList.push_back(this);
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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68 : _params(p)
69{
70#ifdef DEBUG
71 doDebugBreak = false;
72#endif
73
74 doRecordEvent = !Stats::event_ignore.match(name());
75 simObjectList.push_back(this);
76 state = Atomic;
76}
77
78//
79// SimObject constructor: used to maintain static simObjectList
80//
81SimObject::SimObject(const string &_name)
82 : _params(new Params)
83{
84 _params->name = _name;
85#ifdef DEBUG
86 doDebugBreak = false;
87#endif
88
89 doRecordEvent = !Stats::event_ignore.match(name());
90 simObjectList.push_back(this);
77}
78
79//
80// SimObject constructor: used to maintain static simObjectList
81//
82SimObject::SimObject(const string &_name)
83 : _params(new Params)
84{
85 _params->name = _name;
86#ifdef DEBUG
87 doDebugBreak = false;
88#endif
89
90 doRecordEvent = !Stats::event_ignore.match(name());
91 simObjectList.push_back(this);
92 state = Atomic;
91}
92
93void
94SimObject::connect()
95{
96}
97
98void

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214
215 for (; ri != rend; ++ri) {
216 SimObject *obj = *ri;
217 obj->nameOut(os);
218 obj->serialize(os);
219 }
220}
221
93}
94
95void
96SimObject::connect()
97{
98}
99
100void

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216
217 for (; ri != rend; ++ri) {
218 SimObject *obj = *ri;
219 obj->nameOut(os);
220 obj->serialize(os);
221 }
222}
223
224void
225SimObject::unserializeAll(Checkpoint *cp)
226{
227 SimObjectList::reverse_iterator ri = simObjectList.rbegin();
228 SimObjectList::reverse_iterator rend = simObjectList.rend();
229
230 for (; ri != rend; ++ri) {
231 SimObject *obj = *ri;
232 DPRINTFR(Config, "Unserializing '%s'\n",
233 obj->name());
234 if(cp->sectionExists(obj->name()))
235 obj->unserialize(cp, obj->name());
236 else
237 warn("Not unserializing '%s': no section found in checkpoint.\n",
238 obj->name());
239 }
240}
241
222#ifdef DEBUG
223//
224// static function: flag which objects should have the debugger break
225//
226void
227SimObject::debugObjectBreak(const string &objs)
228{
229 SimObjectList::const_iterator i = simObjectList.begin();

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245
246void
247SimObject::recordEvent(const std::string &stat)
248{
249 if (doRecordEvent)
250 Stats::recordEvent(stat);
251}
252
242#ifdef DEBUG
243//
244// static function: flag which objects should have the debugger break
245//
246void
247SimObject::debugObjectBreak(const string &objs)
248{
249 SimObjectList::const_iterator i = simObjectList.begin();

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265
266void
267SimObject::recordEvent(const std::string &stat)
268{
269 if (doRecordEvent)
270 Stats::recordEvent(stat);
271}
272
273bool
274SimObject::quiesce(Event *quiesce_event)
275{
276 if (state != QuiescedAtomic && state != Atomic) {
277 panic("Must implement your own quiesce function if it is to be used "
278 "in timing mode!");
279 }
280 state = QuiescedAtomic;
281 return false;
282}
283
253void
284void
254SimObject::drain(Serializer *serializer)
285SimObject::resume()
255{
286{
256 serializer->signalDrained();
287 if (state == QuiescedAtomic) {
288 state = Atomic;
289 } else if (state == QuiescedTiming) {
290 state = Timing;
291 }
257}
258
292}
293
294void
295SimObject::setMemoryMode(State new_mode)
296{
297 assert(new_mode == Timing || new_mode == Atomic);
298 if (state == QuiescedAtomic && new_mode == Timing) {
299 state = QuiescedTiming;
300 } else if (state == QuiescedTiming && new_mode == Atomic) {
301 state = QuiescedAtomic;
302 } else {
303 state = new_mode;
304 }
305}
306
307void
308SimObject::switchOut()
309{
310 panic("Unimplemented!");
311}
312
313void
314SimObject::takeOverFrom(BaseCPU *cpu)
315{
316 panic("Unimplemented!");
317}
318
259DEFINE_SIM_OBJECT_CLASS_NAME("SimObject", SimObject)
319DEFINE_SIM_OBJECT_CLASS_NAME("SimObject", SimObject)