1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 59 unchanged lines hidden (view full) --- 68 : _params(p) 69{ 70#ifdef DEBUG 71 doDebugBreak = false; 72#endif 73 74 doRecordEvent = !Stats::event_ignore.match(name()); 75 simObjectList.push_back(this); |
76 state = Atomic; |
77} 78 79// 80// SimObject constructor: used to maintain static simObjectList 81// 82SimObject::SimObject(const string &_name) 83 : _params(new Params) 84{ 85 _params->name = _name; 86#ifdef DEBUG 87 doDebugBreak = false; 88#endif 89 90 doRecordEvent = !Stats::event_ignore.match(name()); 91 simObjectList.push_back(this); |
92 state = Atomic; |
93} 94 95void 96SimObject::connect() 97{ 98} 99 100void --- 115 unchanged lines hidden (view full) --- 216 217 for (; ri != rend; ++ri) { 218 SimObject *obj = *ri; 219 obj->nameOut(os); 220 obj->serialize(os); 221 } 222} 223 |
224void 225SimObject::unserializeAll(Checkpoint *cp) 226{ 227 SimObjectList::reverse_iterator ri = simObjectList.rbegin(); 228 SimObjectList::reverse_iterator rend = simObjectList.rend(); 229 230 for (; ri != rend; ++ri) { 231 SimObject *obj = *ri; 232 DPRINTFR(Config, "Unserializing '%s'\n", 233 obj->name()); 234 if(cp->sectionExists(obj->name())) 235 obj->unserialize(cp, obj->name()); 236 else 237 warn("Not unserializing '%s': no section found in checkpoint.\n", 238 obj->name()); 239 } 240} 241 |
242#ifdef DEBUG 243// 244// static function: flag which objects should have the debugger break 245// 246void 247SimObject::debugObjectBreak(const string &objs) 248{ 249 SimObjectList::const_iterator i = simObjectList.begin(); --- 16 unchanged lines hidden (view full) --- 266 267void 268SimObject::recordEvent(const std::string &stat) 269{ 270 if (doRecordEvent) 271 Stats::recordEvent(stat); 272} 273 |
274bool 275SimObject::quiesce(Event *quiesce_event) 276{ 277 if (state != QuiescedAtomic && state != Atomic) { 278 panic("Must implement your own quiesce function if it is to be used " 279 "in timing mode!"); 280 } 281 state = QuiescedAtomic; 282 return false; 283} 284 |
285void |
286SimObject::resume() |
287{ |
288 if (state == QuiescedAtomic) { 289 state = Atomic; 290 } else if (state == QuiescedTiming) { 291 state = Timing; 292 } |
293} 294 |
295void 296SimObject::setMemoryMode(State new_mode) 297{ 298 assert(new_mode == Timing || new_mode == Atomic); 299 if (state == QuiescedAtomic && new_mode == Timing) { 300 state = QuiescedTiming; 301 } else if (state == QuiescedTiming && new_mode == Atomic) { 302 state = QuiescedAtomic; 303 } else { 304 state = new_mode; 305 } 306} 307 308void 309SimObject::switchOut() 310{ 311 panic("Unimplemented!"); 312} 313 314void 315SimObject::takeOverFrom(BaseCPU *cpu) 316{ 317 panic("Unimplemented!"); 318} 319 |
320DEFINE_SIM_OBJECT_CLASS_NAME("SimObject", SimObject) |