1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * Copyright (c) 2011 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Nathan Binkert
30 * Steve Reinhardt
31 * Gabe Black
32 */
33
34#include "base/misc.hh"
35#include "config/the_isa.hh"
36#include "debug/TimeSync.hh"
37#include "sim/full_system.hh"
38#include "sim/root.hh"
39
40Root *Root::_root = NULL;
41
42/*
43 * This function is called periodically by an event in M5 and ensures that
44 * at least as much real time has passed between invocations as simulated time.
45 * If not, the function either sleeps, or if the difference is small enough
46 * spin waits.
47 */
48void
49Root::timeSync()
50{
51 Time cur_time, diff, period = timeSyncPeriod();
52
53 do {
54 cur_time.setTimer();
55 diff = cur_time - lastTime;
56 Time remainder = period - diff;
57 if (diff < period && remainder > _spinThreshold) {
58 DPRINTF(TimeSync, "Sleeping to sync with real time.\n");
59 // Sleep until the end of the period, or until a signal.
60 sleep(remainder);
61 // Refresh the current time.
62 cur_time.setTimer();
63 }
64 } while (diff < period);
65 lastTime = cur_time;
66 schedule(&syncEvent, curTick() + _periodTick);
67}
68
69void
70Root::timeSyncEnable(bool en)
71{
72 if (en == _enabled)
73 return;
74 _enabled = en;
75 if (_enabled) {
76 // Get event going.
77 Tick periods = ((curTick() + _periodTick - 1) / _periodTick);
78 Tick nextPeriod = periods * _periodTick;
79 schedule(&syncEvent, nextPeriod);
80 } else {
81 // Stop event.
82 deschedule(&syncEvent);
83 }
84}
85
86/// Configure the period for time sync events.
87void
88Root::timeSyncPeriod(Time newPeriod)
89{
90 bool en = timeSyncEnabled();
91 _period = newPeriod;
92 _periodTick = _period.getTick();
93 timeSyncEnable(en);
94}
95
96/// Set the threshold for time remaining to spin wait.
97void
98Root::timeSyncSpinThreshold(Time newThreshold)
99{
100 bool en = timeSyncEnabled();
101 _spinThreshold = newThreshold;
102 timeSyncEnable(en);
103}
104
105Root::Root(RootParams *p) : SimObject(p), _enabled(false),
106 _periodTick(p->time_sync_period), syncEvent(this)
107{
108 _period.setTick(p->time_sync_period);
109 _spinThreshold.setTick(p->time_sync_spin_threshold);
110
111 assert(_root == NULL);
112 _root = this;
113 lastTime.setTimer();
114}
115
116void
117Root::initState()
118{
119 timeSyncEnable(params()->time_sync_enable);
120}
121
122void
123Root::loadState(Checkpoint *cp)
124{
125 SimObject::loadState(cp);
126 timeSyncEnable(params()->time_sync_enable);
127}
128
129void
130Root::serialize(std::ostream &os)
131{
132 uint64_t cpt_ver = gem5CheckpointVersion;
133 SERIALIZE_SCALAR(cpt_ver);
134 SERIALIZE_SCALAR(FullSystem);
135 std::string isa = THE_ISA_STR;
136 SERIALIZE_SCALAR(isa);
137}
138
139void
140Root::unserialize(Checkpoint *cp, const std::string &section)
141{
142 uint64_t cpt_ver = 0;
143 UNSERIALIZE_OPT_SCALAR(cpt_ver);
144 if (cpt_ver < gem5CheckpointVersion) {
145 warn("**********************************************************\n");
146 warn("!!!! Checkpoint ver %#x is older than current ver %#x !!!!\n",
147 cpt_ver, gem5CheckpointVersion);
148 warn("You might experience some issues when restoring and should run "
149 "the checkpoint upgrader (util/cpt_upgrader.py) on your "
150 "checkpoint\n");
151 warn("**********************************************************\n");
152 } else if (cpt_ver > gem5CheckpointVersion) {
153 warn("**********************************************************\n");
154 warn("!!!! Checkpoint ver %#x is newer than current ver %#x !!!!\n",
155 cpt_ver, gem5CheckpointVersion);
156 warn("Running a new checkpoint with an older version of gem5 is not "
157 "supported. While it might work, you may experience incorrect "
158 "behavior or crashes.\n");
159 warn("**********************************************************\n");
160 }
161}
162
163
164bool FullSystem;
165unsigned int FullSystemInt;
166
167Root *
168RootParams::create()
169{
170 static bool created = false;
171 if (created)
172 panic("only one root object allowed!");
173
174 created = true;
175
176 FullSystem = full_system;
177 FullSystemInt = full_system ? 1 : 0;
178
179 return new Root(this);
180}