1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 31 unchanged lines hidden (view full) --- 40 41/** 42 * @todo these externs are only here for a hack in fullCPU::takeOver... 43 */ 44extern bool doStatisticsInsts; 45extern bool doCheckpointInsts; 46extern bool doQuiesce; 47 |
48void arm(ThreadContext *tc); 49void quiesce(ThreadContext *tc); 50void quiesceSkip(ThreadContext *tc); 51void quiesceNs(ThreadContext *tc, uint64_t ns); 52void quiesceCycles(ThreadContext *tc, uint64_t cycles); 53uint64_t quiesceTime(ThreadContext *tc); 54uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, 55 uint64_t offset); |
56void loadsymbol(ThreadContext *xc); 57void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); 58uint64_t initParam(ThreadContext *xc); |
59uint64_t rpns(ThreadContext *tc); 60void wakeCPU(ThreadContext *tc, uint64_t cpuid); 61void m5exit(ThreadContext *tc, Tick delay); 62void resetstats(ThreadContext *tc, Tick delay, Tick period); 63void dumpstats(ThreadContext *tc, Tick delay, Tick period); 64void dumpresetstats(ThreadContext *tc, Tick delay, Tick period); 65void m5checkpoint(ThreadContext *tc, Tick delay, Tick period); 66void debugbreak(ThreadContext *tc); 67void switchcpu(ThreadContext *tc); 68void workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid); 69void workend(ThreadContext *tc, uint64_t workid, uint64_t threadid); 70 71} // namespace PseudoInst 72 73#endif // __SIM_PSEUDO_INST_HH__ |