insttracer.hh (12386:2bf5fb25a5f1) insttracer.hh (13610:5d5404ac6288)
1/*
1/*
2 * Copyright (c) 2014 ARM Limited
2 * Copyright (c) 2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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39 *
40 * Authors: Steve Reinhardt
41 * Nathan Binkert
42 */
43
44#ifndef __INSTRECORD_HH__
45#define __INSTRECORD_HH__
46
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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39 *
40 * Authors: Steve Reinhardt
41 * Nathan Binkert
42 */
43
44#ifndef __INSTRECORD_HH__
45#define __INSTRECORD_HH__
46
47#include "arch/generic/vec_pred_reg.hh"
48#include "arch/generic/vec_reg.hh"
47#include "base/types.hh"
48#include "cpu/inst_seq.hh"
49#include "cpu/static_inst.hh"
50#include "sim/sim_object.hh"
51
52class ThreadContext;
53
54namespace Trace {

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90 * since many instructions write multiple values (e.g. destintation
91 * register, flags, status, ...) This only captures the last write.
92 * @TODO fix this and record all destintations that an instruction writes
93 * @see data_status
94 */
95 union {
96 uint64_t as_int;
97 double as_double;
49#include "base/types.hh"
50#include "cpu/inst_seq.hh"
51#include "cpu/static_inst.hh"
52#include "sim/sim_object.hh"
53
54class ThreadContext;
55
56namespace Trace {

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92 * since many instructions write multiple values (e.g. destintation
93 * register, flags, status, ...) This only captures the last write.
94 * @TODO fix this and record all destintations that an instruction writes
95 * @see data_status
96 */
97 union {
98 uint64_t as_int;
99 double as_double;
100 ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;
101 ::VecPredRegContainer<TheISA::VecPredRegSizeBits,
102 TheISA::VecPredRegHasPackedRepr>* as_pred;
98 } data;
99
100 /** @defgroup fetch_seq
101 * This records the serial number that the instruction was fetched in.
102 * @see fetch_seq_valid
103 */
104 InstSeqNum fetch_seq;
105

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113 * What size of data was written?
114 */
115 enum DataStatus {
116 DataInvalid = 0,
117 DataInt8 = 1, // set to equal number of bytes
118 DataInt16 = 2,
119 DataInt32 = 4,
120 DataInt64 = 8,
103 } data;
104
105 /** @defgroup fetch_seq
106 * This records the serial number that the instruction was fetched in.
107 * @see fetch_seq_valid
108 */
109 InstSeqNum fetch_seq;
110

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118 * What size of data was written?
119 */
120 enum DataStatus {
121 DataInvalid = 0,
122 DataInt8 = 1, // set to equal number of bytes
123 DataInt16 = 2,
124 DataInt32 = 4,
125 DataInt64 = 8,
121 DataDouble = 3
126 DataDouble = 3,
127 DataVec = 5,
128 DataVecPred = 6
122 } data_status;
123
124 /** @ingroup memory
125 * Are the memory fields in the record valid?
126 */
127 bool mem_valid;
128
129 /** @ingroup fetch_seq

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145 TheISA::PCState _pc,
146 const StaticInstPtr _macroStaticInst = NULL)
147 : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
148 macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
149 fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
150 fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
151 { }
152
129 } data_status;
130
131 /** @ingroup memory
132 * Are the memory fields in the record valid?
133 */
134 bool mem_valid;
135
136 /** @ingroup fetch_seq

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152 TheISA::PCState _pc,
153 const StaticInstPtr _macroStaticInst = NULL)
154 : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc),
155 macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0),
156 fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false),
157 fetch_seq_valid(false), cp_seq_valid(false), predicate(true)
158 { }
159
153 virtual ~InstRecord() { }
160 virtual ~InstRecord()
161 {
162 if (data_status == DataVec) {
163 assert(data.as_vec);
164 delete data.as_vec;
165 } else if (data_status == DataVecPred) {
166 assert(data.as_pred);
167 delete data.as_pred;
168 }
169 }
154
155 void setWhen(Tick new_when) { when = new_when; }
156 void setMem(Addr a, Addr s, unsigned f)
157 {
158 addr = a; size = s; flags = f; mem_valid = true;
159 }
160
161 template <typename T, size_t N>

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176
177 void setData(int64_t d) { setData((uint64_t)d); }
178 void setData(int32_t d) { setData((uint32_t)d); }
179 void setData(int16_t d) { setData((uint16_t)d); }
180 void setData(int8_t d) { setData((uint8_t)d); }
181
182 void setData(double d) { data.as_double = d; data_status = DataDouble; }
183
170
171 void setWhen(Tick new_when) { when = new_when; }
172 void setMem(Addr a, Addr s, unsigned f)
173 {
174 addr = a; size = s; flags = f; mem_valid = true;
175 }
176
177 template <typename T, size_t N>

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192
193 void setData(int64_t d) { setData((uint64_t)d); }
194 void setData(int32_t d) { setData((uint32_t)d); }
195 void setData(int16_t d) { setData((uint16_t)d); }
196 void setData(int8_t d) { setData((uint8_t)d); }
197
198 void setData(double d) { data.as_double = d; data_status = DataDouble; }
199
200 void
201 setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d)
202 {
203 data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d);
204 data_status = DataVec;
205 }
206
207 void
208 setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits,
209 TheISA::VecPredRegHasPackedRepr>& d)
210 {
211 data.as_pred = new ::VecPredRegContainer<
212 TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr>(d);
213 data_status = DataVecPred;
214 }
215
184 void setFetchSeq(InstSeqNum seq)
185 { fetch_seq = seq; fetch_seq_valid = true; }
186
187 void setCPSeq(InstSeqNum seq)
188 { cp_seq = seq; cp_seq_valid = true; }
189
190 void setPredicate(bool val) { predicate = val; }
191

--- 45 unchanged lines hidden --- 		216 void setFetchSeq(InstSeqNum seq)
217 { fetch_seq = seq; fetch_seq_valid = true; }
218
219 void setCPSeq(InstSeqNum seq)
220 { cp_seq = seq; cp_seq_valid = true; }
221
222 void setPredicate(bool val) { predicate = val; }
223

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