1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 82 unchanged lines hidden (view full) --- 91 InstRecord(Tick _when, ThreadContext *_thread, 92 const StaticInstPtr _staticInst, 93 Addr _pc, bool spec, 94 const StaticInstPtr _macroStaticInst = NULL, 95 MicroPC _upc = 0) 96 : when(_when), thread(_thread), 97 staticInst(_staticInst), PC(_pc), 98 macroStaticInst(_macroStaticInst), upc(_upc), |
99 misspeculating(spec), predicate(true) |
100 { 101 data_status = DataInvalid; 102 addr_valid = false; 103 104 fetch_seq_valid = false; 105 cp_seq_valid = false; |
106 } 107 108 virtual ~InstRecord() { } 109 110 void setAddr(Addr a) { addr = a; addr_valid = true; } 111 112 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } 113 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; } --- 66 unchanged lines hidden --- |