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< * Copyright (c) 2014 ARM Limited
---
> * Copyright (c) 2014, 2017 ARM Limited
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> #include "arch/generic/vec_pred_reg.hh"
> #include "arch/generic/vec_reg.hh"
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> ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;
> ::VecPredRegContainer<TheISA::VecPredRegSizeBits,
> TheISA::VecPredRegHasPackedRepr>* as_pred;
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< DataDouble = 3
---
> DataDouble = 3,
> DataVec = 5,
> DataVecPred = 6
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< virtual ~InstRecord() { }
---
> virtual ~InstRecord()
> {
> if (data_status == DataVec) {
> assert(data.as_vec);
> delete data.as_vec;
> } else if (data_status == DataVecPred) {
> assert(data.as_pred);
> delete data.as_pred;
> }
> }
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> void
> setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d)
> {
> data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d);
> data_status = DataVec;
> }
>
> void
> setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits,
> TheISA::VecPredRegHasPackedRepr>& d)
> {
> data.as_pred = new ::VecPredRegContainer<
> TheISA::VecPredRegSizeBits, TheISA::VecPredRegHasPackedRepr>(d);
> data_status = DataVecPred;
> }
>