1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __INSTRECORD_HH__ 33#define __INSTRECORD_HH__ 34 35#include "base/bigint.hh" 36#include "base/trace.hh" 37#include "base/types.hh" 38#include "cpu/inst_seq.hh" // for InstSeqNum 39#include "cpu/static_inst.hh" 40#include "sim/sim_object.hh" 41 42class ThreadContext; 43 44namespace Trace { 45 46class InstRecord 47{ 48 protected: 49 Tick when; 50 51 // The following fields are initialized by the constructor and 52 // thus guaranteed to be valid. 53 ThreadContext *thread; 54 // need to make this ref-counted so it doesn't go away before we 55 // dump the record 56 StaticInstPtr staticInst; 57 TheISA::PCState pc; 58 StaticInstPtr macroStaticInst; 59 bool misspeculating; 60 bool predicate; 61 62 // The remaining fields are only valid for particular instruction 63 // types (e.g, addresses for memory ops) or when particular 64 // options are enabled (e.g., tracing full register contents). 65 // Each data field has an associated valid flag to indicate 66 // whether the data field is valid. 67 Addr addr; 68 bool addr_valid; 69 70 union { 71 uint64_t as_int; 72 double as_double; 73 } data; 74 enum { 75 DataInvalid = 0, 76 DataInt8 = 1, // set to equal number of bytes 77 DataInt16 = 2, 78 DataInt32 = 4, 79 DataInt64 = 8, 80 DataDouble = 3 81 } data_status; 82 83 InstSeqNum fetch_seq; 84 bool fetch_seq_valid; 85 86 InstSeqNum cp_seq; 87 bool cp_seq_valid; 88 89 public: 90 InstRecord(Tick _when, ThreadContext *_thread, 91 const StaticInstPtr _staticInst, 92 TheISA::PCState _pc, bool spec, 93 const StaticInstPtr _macroStaticInst = NULL) 94 : when(_when), thread(_thread), 95 staticInst(_staticInst), pc(_pc), 96 macroStaticInst(_macroStaticInst), 97 misspeculating(spec), predicate(true) 98 { 99 data_status = DataInvalid; 100 addr_valid = false; 101 102 fetch_seq_valid = false; 103 cp_seq_valid = false; 104 } 105 106 virtual ~InstRecord() { } 107 108 void setAddr(Addr a) { addr = a; addr_valid = true; } 109 110 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } 111 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; } 112 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 113 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 114 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 115 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 116 117 void setData(int64_t d) { setData((uint64_t)d); } 118 void setData(int32_t d) { setData((uint32_t)d); } 119 void setData(int16_t d) { setData((uint16_t)d); } 120 void setData(int8_t d) { setData((uint8_t)d); } 121 122 void setData(double d) { data.as_double = d; data_status = DataDouble; } 123 124 void setFetchSeq(InstSeqNum seq) 125 { fetch_seq = seq; fetch_seq_valid = true; } 126 127 void setCPSeq(InstSeqNum seq) 128 { cp_seq = seq; cp_seq_valid = true; } 129 130 void setPredicate(bool val) { predicate = val; } 131 132 virtual void dump() = 0; 133 134 public: 135 Tick getWhen() { return when; } 136 ThreadContext *getThread() { return thread; } 137 StaticInstPtr getStaticInst() { return staticInst; } 138 TheISA::PCState getPCState() { return pc; } 139 StaticInstPtr getMacroStaticInst() { return macroStaticInst; } 140 bool getMisspeculating() { return misspeculating; } 141 142 Addr getAddr() { return addr; } 143 bool getAddrValid() { return addr_valid; } 144 145 uint64_t getIntData() { return data.as_int; } 146 double getFloatData() { return data.as_double; } 147 int getDataStatus() { return data_status; } 148 149 InstSeqNum getFetchSeq() { return fetch_seq; } 150 bool getFetchSeqValid() { return fetch_seq_valid; } 151 152 InstSeqNum getCpSeq() { return cp_seq; } 153 bool getCpSeqValid() { return cp_seq_valid; } 154}; 155 156class InstTracer : public SimObject 157{ 158 public: 159 InstTracer(const Params *p) : SimObject(p) 160 {} 161 162 virtual ~InstTracer() 163 {}; 164 165 virtual InstRecord * 166 getInstRecord(Tick when, ThreadContext *tc, 167 const StaticInstPtr staticInst, TheISA::PCState pc, 168 const StaticInstPtr macroStaticInst = NULL) = 0; 169}; 170 171 172
| 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __INSTRECORD_HH__ 33#define __INSTRECORD_HH__ 34 35#include "base/bigint.hh" 36#include "base/trace.hh" 37#include "base/types.hh" 38#include "cpu/inst_seq.hh" // for InstSeqNum 39#include "cpu/static_inst.hh" 40#include "sim/sim_object.hh" 41 42class ThreadContext; 43 44namespace Trace { 45 46class InstRecord 47{ 48 protected: 49 Tick when; 50 51 // The following fields are initialized by the constructor and 52 // thus guaranteed to be valid. 53 ThreadContext *thread; 54 // need to make this ref-counted so it doesn't go away before we 55 // dump the record 56 StaticInstPtr staticInst; 57 TheISA::PCState pc; 58 StaticInstPtr macroStaticInst; 59 bool misspeculating; 60 bool predicate; 61 62 // The remaining fields are only valid for particular instruction 63 // types (e.g, addresses for memory ops) or when particular 64 // options are enabled (e.g., tracing full register contents). 65 // Each data field has an associated valid flag to indicate 66 // whether the data field is valid. 67 Addr addr; 68 bool addr_valid; 69 70 union { 71 uint64_t as_int; 72 double as_double; 73 } data; 74 enum { 75 DataInvalid = 0, 76 DataInt8 = 1, // set to equal number of bytes 77 DataInt16 = 2, 78 DataInt32 = 4, 79 DataInt64 = 8, 80 DataDouble = 3 81 } data_status; 82 83 InstSeqNum fetch_seq; 84 bool fetch_seq_valid; 85 86 InstSeqNum cp_seq; 87 bool cp_seq_valid; 88 89 public: 90 InstRecord(Tick _when, ThreadContext *_thread, 91 const StaticInstPtr _staticInst, 92 TheISA::PCState _pc, bool spec, 93 const StaticInstPtr _macroStaticInst = NULL) 94 : when(_when), thread(_thread), 95 staticInst(_staticInst), pc(_pc), 96 macroStaticInst(_macroStaticInst), 97 misspeculating(spec), predicate(true) 98 { 99 data_status = DataInvalid; 100 addr_valid = false; 101 102 fetch_seq_valid = false; 103 cp_seq_valid = false; 104 } 105 106 virtual ~InstRecord() { } 107 108 void setAddr(Addr a) { addr = a; addr_valid = true; } 109 110 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } 111 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; } 112 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 113 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 114 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 115 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 116 117 void setData(int64_t d) { setData((uint64_t)d); } 118 void setData(int32_t d) { setData((uint32_t)d); } 119 void setData(int16_t d) { setData((uint16_t)d); } 120 void setData(int8_t d) { setData((uint8_t)d); } 121 122 void setData(double d) { data.as_double = d; data_status = DataDouble; } 123 124 void setFetchSeq(InstSeqNum seq) 125 { fetch_seq = seq; fetch_seq_valid = true; } 126 127 void setCPSeq(InstSeqNum seq) 128 { cp_seq = seq; cp_seq_valid = true; } 129 130 void setPredicate(bool val) { predicate = val; } 131 132 virtual void dump() = 0; 133 134 public: 135 Tick getWhen() { return when; } 136 ThreadContext *getThread() { return thread; } 137 StaticInstPtr getStaticInst() { return staticInst; } 138 TheISA::PCState getPCState() { return pc; } 139 StaticInstPtr getMacroStaticInst() { return macroStaticInst; } 140 bool getMisspeculating() { return misspeculating; } 141 142 Addr getAddr() { return addr; } 143 bool getAddrValid() { return addr_valid; } 144 145 uint64_t getIntData() { return data.as_int; } 146 double getFloatData() { return data.as_double; } 147 int getDataStatus() { return data_status; } 148 149 InstSeqNum getFetchSeq() { return fetch_seq; } 150 bool getFetchSeqValid() { return fetch_seq_valid; } 151 152 InstSeqNum getCpSeq() { return cp_seq; } 153 bool getCpSeqValid() { return cp_seq_valid; } 154}; 155 156class InstTracer : public SimObject 157{ 158 public: 159 InstTracer(const Params *p) : SimObject(p) 160 {} 161 162 virtual ~InstTracer() 163 {}; 164 165 virtual InstRecord * 166 getInstRecord(Tick when, ThreadContext *tc, 167 const StaticInstPtr staticInst, TheISA::PCState pc, 168 const StaticInstPtr macroStaticInst = NULL) = 0; 169}; 170 171 172
|