1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __INSTRECORD_HH__ 33#define __INSTRECORD_HH__ 34 35#include "base/bigint.hh" 36#include "base/trace.hh" 37#include "base/types.hh" 38#include "cpu/inst_seq.hh" // for InstSeqNum 39#include "cpu/static_inst.hh" 40#include "sim/sim_object.hh" 41 42class ThreadContext; 43 44namespace Trace { 45 46class InstRecord 47{ 48 protected: 49 Tick when; 50 51 // The following fields are initialized by the constructor and 52 // thus guaranteed to be valid. 53 ThreadContext *thread; 54 // need to make this ref-counted so it doesn't go away before we 55 // dump the record 56 StaticInstPtr staticInst; 57 Addr PC; 58 StaticInstPtr macroStaticInst; 59 MicroPC upc; 60 bool misspeculating; 61 bool predicate; 62 63 // The remaining fields are only valid for particular instruction 64 // types (e.g, addresses for memory ops) or when particular 65 // options are enabled (e.g., tracing full register contents). 66 // Each data field has an associated valid flag to indicate 67 // whether the data field is valid. 68 Addr addr; 69 bool addr_valid; 70 71 union { 72 uint64_t as_int; 73 double as_double; 74 } data; 75 enum { 76 DataInvalid = 0, 77 DataInt8 = 1, // set to equal number of bytes 78 DataInt16 = 2, 79 DataInt32 = 4, 80 DataInt64 = 8, 81 DataDouble = 3 82 } data_status; 83 84 InstSeqNum fetch_seq; 85 bool fetch_seq_valid; 86 87 InstSeqNum cp_seq; 88 bool cp_seq_valid; 89 90 public: 91 InstRecord(Tick _when, ThreadContext *_thread, 92 const StaticInstPtr _staticInst, 93 Addr _pc, bool spec, 94 const StaticInstPtr _macroStaticInst = NULL, 95 MicroPC _upc = 0) 96 : when(_when), thread(_thread), 97 staticInst(_staticInst), PC(_pc), 98 macroStaticInst(_macroStaticInst), upc(_upc),
| 1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Nathan Binkert 30 */ 31 32#ifndef __INSTRECORD_HH__ 33#define __INSTRECORD_HH__ 34 35#include "base/bigint.hh" 36#include "base/trace.hh" 37#include "base/types.hh" 38#include "cpu/inst_seq.hh" // for InstSeqNum 39#include "cpu/static_inst.hh" 40#include "sim/sim_object.hh" 41 42class ThreadContext; 43 44namespace Trace { 45 46class InstRecord 47{ 48 protected: 49 Tick when; 50 51 // The following fields are initialized by the constructor and 52 // thus guaranteed to be valid. 53 ThreadContext *thread; 54 // need to make this ref-counted so it doesn't go away before we 55 // dump the record 56 StaticInstPtr staticInst; 57 Addr PC; 58 StaticInstPtr macroStaticInst; 59 MicroPC upc; 60 bool misspeculating; 61 bool predicate; 62 63 // The remaining fields are only valid for particular instruction 64 // types (e.g, addresses for memory ops) or when particular 65 // options are enabled (e.g., tracing full register contents). 66 // Each data field has an associated valid flag to indicate 67 // whether the data field is valid. 68 Addr addr; 69 bool addr_valid; 70 71 union { 72 uint64_t as_int; 73 double as_double; 74 } data; 75 enum { 76 DataInvalid = 0, 77 DataInt8 = 1, // set to equal number of bytes 78 DataInt16 = 2, 79 DataInt32 = 4, 80 DataInt64 = 8, 81 DataDouble = 3 82 } data_status; 83 84 InstSeqNum fetch_seq; 85 bool fetch_seq_valid; 86 87 InstSeqNum cp_seq; 88 bool cp_seq_valid; 89 90 public: 91 InstRecord(Tick _when, ThreadContext *_thread, 92 const StaticInstPtr _staticInst, 93 Addr _pc, bool spec, 94 const StaticInstPtr _macroStaticInst = NULL, 95 MicroPC _upc = 0) 96 : when(_when), thread(_thread), 97 staticInst(_staticInst), PC(_pc), 98 macroStaticInst(_macroStaticInst), upc(_upc),
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107 } 108 109 virtual ~InstRecord() { } 110 111 void setAddr(Addr a) { addr = a; addr_valid = true; } 112 113 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } 114 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; } 115 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 116 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 117 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 118 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 119 120 void setData(int64_t d) { setData((uint64_t)d); } 121 void setData(int32_t d) { setData((uint32_t)d); } 122 void setData(int16_t d) { setData((uint16_t)d); } 123 void setData(int8_t d) { setData((uint8_t)d); } 124 125 void setData(double d) { data.as_double = d; data_status = DataDouble; } 126 127 void setFetchSeq(InstSeqNum seq) 128 { fetch_seq = seq; fetch_seq_valid = true; } 129 130 void setCPSeq(InstSeqNum seq) 131 { cp_seq = seq; cp_seq_valid = true; } 132 133 void setPredicate(bool val) { predicate = val; } 134 135 virtual void dump() = 0; 136 137 public: 138 Tick getWhen() { return when; } 139 ThreadContext *getThread() { return thread; } 140 StaticInstPtr getStaticInst() { return staticInst; } 141 Addr getPC() { return PC; } 142 StaticInstPtr getMacroStaticInst() { return macroStaticInst; } 143 MicroPC getUPC() { return upc; } 144 bool getMisspeculating() { return misspeculating; } 145 146 Addr getAddr() { return addr; } 147 bool getAddrValid() { return addr_valid; } 148 149 uint64_t getIntData() { return data.as_int; } 150 double getFloatData() { return data.as_double; } 151 int getDataStatus() { return data_status; } 152 153 InstSeqNum getFetchSeq() { return fetch_seq; } 154 bool getFetchSeqValid() { return fetch_seq_valid; } 155 156 InstSeqNum getCpSeq() { return cp_seq; } 157 bool getCpSeqValid() { return cp_seq_valid; } 158}; 159 160class InstTracer : public SimObject 161{ 162 public: 163 InstTracer(const Params *p) : SimObject(p) 164 {} 165 166 virtual ~InstTracer() 167 {}; 168 169 virtual InstRecord * 170 getInstRecord(Tick when, ThreadContext *tc, 171 const StaticInstPtr staticInst, Addr pc, 172 const StaticInstPtr macroStaticInst = NULL, 173 MicroPC _upc = 0) = 0; 174}; 175 176 177 178}; // namespace Trace 179 180#endif // __INSTRECORD_HH__
| 106 } 107 108 virtual ~InstRecord() { } 109 110 void setAddr(Addr a) { addr = a; addr_valid = true; } 111 112 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } 113 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; } 114 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 115 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 116 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 117 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 118 119 void setData(int64_t d) { setData((uint64_t)d); } 120 void setData(int32_t d) { setData((uint32_t)d); } 121 void setData(int16_t d) { setData((uint16_t)d); } 122 void setData(int8_t d) { setData((uint8_t)d); } 123 124 void setData(double d) { data.as_double = d; data_status = DataDouble; } 125 126 void setFetchSeq(InstSeqNum seq) 127 { fetch_seq = seq; fetch_seq_valid = true; } 128 129 void setCPSeq(InstSeqNum seq) 130 { cp_seq = seq; cp_seq_valid = true; } 131 132 void setPredicate(bool val) { predicate = val; } 133 134 virtual void dump() = 0; 135 136 public: 137 Tick getWhen() { return when; } 138 ThreadContext *getThread() { return thread; } 139 StaticInstPtr getStaticInst() { return staticInst; } 140 Addr getPC() { return PC; } 141 StaticInstPtr getMacroStaticInst() { return macroStaticInst; } 142 MicroPC getUPC() { return upc; } 143 bool getMisspeculating() { return misspeculating; } 144 145 Addr getAddr() { return addr; } 146 bool getAddrValid() { return addr_valid; } 147 148 uint64_t getIntData() { return data.as_int; } 149 double getFloatData() { return data.as_double; } 150 int getDataStatus() { return data_status; } 151 152 InstSeqNum getFetchSeq() { return fetch_seq; } 153 bool getFetchSeqValid() { return fetch_seq_valid; } 154 155 InstSeqNum getCpSeq() { return cp_seq; } 156 bool getCpSeqValid() { return cp_seq_valid; } 157}; 158 159class InstTracer : public SimObject 160{ 161 public: 162 InstTracer(const Params *p) : SimObject(p) 163 {} 164 165 virtual ~InstTracer() 166 {}; 167 168 virtual InstRecord * 169 getInstRecord(Tick when, ThreadContext *tc, 170 const StaticInstPtr staticInst, Addr pc, 171 const StaticInstPtr macroStaticInst = NULL, 172 MicroPC _upc = 0) = 0; 173}; 174 175 176 177}; // namespace Trace 178 179#endif // __INSTRECORD_HH__
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