1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __INSTRECORD_HH__
33#define __INSTRECORD_HH__
34
35#include "base/bigint.hh"
36#include "base/trace.hh"
37#include "cpu/inst_seq.hh" // for InstSeqNum
38#include "cpu/static_inst.hh"
| 1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Nathan Binkert
30 */
31
32#ifndef __INSTRECORD_HH__
33#define __INSTRECORD_HH__
34
35#include "base/bigint.hh"
36#include "base/trace.hh"
37#include "cpu/inst_seq.hh" // for InstSeqNum
38#include "cpu/static_inst.hh"
|
40#include "sim/sim_object.hh"
41
42class ThreadContext;
43
44namespace Trace {
45
46class InstRecord
47{
48 protected:
49 Tick when;
50
51 // The following fields are initialized by the constructor and
52 // thus guaranteed to be valid.
53 ThreadContext *thread;
54 // need to make this ref-counted so it doesn't go away before we
55 // dump the record
56 StaticInstPtr staticInst;
57 Addr PC;
58 StaticInstPtr macroStaticInst;
59 MicroPC upc;
60 bool misspeculating;
61
62 // The remaining fields are only valid for particular instruction
63 // types (e.g, addresses for memory ops) or when particular
64 // options are enabled (e.g., tracing full register contents).
65 // Each data field has an associated valid flag to indicate
66 // whether the data field is valid.
67 Addr addr;
68 bool addr_valid;
69
70 union {
71 uint64_t as_int;
72 double as_double;
73 } data;
74 enum {
75 DataInvalid = 0,
76 DataInt8 = 1, // set to equal number of bytes
77 DataInt16 = 2,
78 DataInt32 = 4,
79 DataInt64 = 8,
80 DataDouble = 3
81 } data_status;
82
83 InstSeqNum fetch_seq;
84 bool fetch_seq_valid;
85
86 InstSeqNum cp_seq;
87 bool cp_seq_valid;
88
89 public:
90 InstRecord(Tick _when, ThreadContext *_thread,
91 const StaticInstPtr _staticInst,
92 Addr _pc, bool spec,
93 const StaticInstPtr _macroStaticInst = NULL,
94 MicroPC _upc = 0)
95 : when(_when), thread(_thread),
96 staticInst(_staticInst), PC(_pc),
97 macroStaticInst(_macroStaticInst), upc(_upc),
98 misspeculating(spec)
99 {
100 data_status = DataInvalid;
101 addr_valid = false;
102
103 fetch_seq_valid = false;
104 cp_seq_valid = false;
105 }
106
107 virtual ~InstRecord() { }
108
109 void setAddr(Addr a) { addr = a; addr_valid = true; }
110
111 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
112 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
113 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
114 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
115 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
116 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
117
118 void setData(int64_t d) { setData((uint64_t)d); }
119 void setData(int32_t d) { setData((uint32_t)d); }
120 void setData(int16_t d) { setData((uint16_t)d); }
121 void setData(int8_t d) { setData((uint8_t)d); }
122
123 void setData(double d) { data.as_double = d; data_status = DataDouble; }
124
125 void setFetchSeq(InstSeqNum seq)
126 { fetch_seq = seq; fetch_seq_valid = true; }
127
128 void setCPSeq(InstSeqNum seq)
129 { cp_seq = seq; cp_seq_valid = true; }
130
131 virtual void dump() = 0;
132};
133
134class InstTracer : public SimObject
135{
136 public:
137 InstTracer(const Params *p) : SimObject(p)
138 {}
139
140 virtual ~InstTracer()
141 {};
142
143 virtual InstRecord *
144 getInstRecord(Tick when, ThreadContext *tc,
145 const StaticInstPtr staticInst, Addr pc,
146 const StaticInstPtr macroStaticInst = NULL,
147 MicroPC _upc = 0) = 0;
148};
149
150
151
152}; // namespace Trace
153
154#endif // __INSTRECORD_HH__
| 40#include "sim/sim_object.hh"
41
42class ThreadContext;
43
44namespace Trace {
45
46class InstRecord
47{
48 protected:
49 Tick when;
50
51 // The following fields are initialized by the constructor and
52 // thus guaranteed to be valid.
53 ThreadContext *thread;
54 // need to make this ref-counted so it doesn't go away before we
55 // dump the record
56 StaticInstPtr staticInst;
57 Addr PC;
58 StaticInstPtr macroStaticInst;
59 MicroPC upc;
60 bool misspeculating;
61
62 // The remaining fields are only valid for particular instruction
63 // types (e.g, addresses for memory ops) or when particular
64 // options are enabled (e.g., tracing full register contents).
65 // Each data field has an associated valid flag to indicate
66 // whether the data field is valid.
67 Addr addr;
68 bool addr_valid;
69
70 union {
71 uint64_t as_int;
72 double as_double;
73 } data;
74 enum {
75 DataInvalid = 0,
76 DataInt8 = 1, // set to equal number of bytes
77 DataInt16 = 2,
78 DataInt32 = 4,
79 DataInt64 = 8,
80 DataDouble = 3
81 } data_status;
82
83 InstSeqNum fetch_seq;
84 bool fetch_seq_valid;
85
86 InstSeqNum cp_seq;
87 bool cp_seq_valid;
88
89 public:
90 InstRecord(Tick _when, ThreadContext *_thread,
91 const StaticInstPtr _staticInst,
92 Addr _pc, bool spec,
93 const StaticInstPtr _macroStaticInst = NULL,
94 MicroPC _upc = 0)
95 : when(_when), thread(_thread),
96 staticInst(_staticInst), PC(_pc),
97 macroStaticInst(_macroStaticInst), upc(_upc),
98 misspeculating(spec)
99 {
100 data_status = DataInvalid;
101 addr_valid = false;
102
103 fetch_seq_valid = false;
104 cp_seq_valid = false;
105 }
106
107 virtual ~InstRecord() { }
108
109 void setAddr(Addr a) { addr = a; addr_valid = true; }
110
111 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
112 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
113 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
114 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
115 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
116 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
117
118 void setData(int64_t d) { setData((uint64_t)d); }
119 void setData(int32_t d) { setData((uint32_t)d); }
120 void setData(int16_t d) { setData((uint16_t)d); }
121 void setData(int8_t d) { setData((uint8_t)d); }
122
123 void setData(double d) { data.as_double = d; data_status = DataDouble; }
124
125 void setFetchSeq(InstSeqNum seq)
126 { fetch_seq = seq; fetch_seq_valid = true; }
127
128 void setCPSeq(InstSeqNum seq)
129 { cp_seq = seq; cp_seq_valid = true; }
130
131 virtual void dump() = 0;
132};
133
134class InstTracer : public SimObject
135{
136 public:
137 InstTracer(const Params *p) : SimObject(p)
138 {}
139
140 virtual ~InstTracer()
141 {};
142
143 virtual InstRecord *
144 getInstRecord(Tick when, ThreadContext *tc,
145 const StaticInstPtr staticInst, Addr pc,
146 const StaticInstPtr macroStaticInst = NULL,
147 MicroPC _upc = 0) = 0;
148};
149
150
151
152}; // namespace Trace
153
154#endif // __INSTRECORD_HH__
|