1/* 2 * Copyright (c) 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathan Binkert 42 */ 43 44#ifndef __INSTRECORD_HH__ 45#define __INSTRECORD_HH__ 46
| 1/* 2 * Copyright (c) 2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2001-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Steve Reinhardt 41 * Nathan Binkert 42 */ 43 44#ifndef __INSTRECORD_HH__ 45#define __INSTRECORD_HH__ 46
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47#include "base/bigint.hh"
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48#include "base/types.hh" 49#include "cpu/inst_seq.hh" 50#include "cpu/static_inst.hh" 51#include "sim/sim_object.hh" 52 53class ThreadContext; 54 55namespace Trace { 56 57class InstRecord 58{ 59 protected: 60 Tick when; 61 62 // The following fields are initialized by the constructor and 63 // thus guaranteed to be valid. 64 ThreadContext *thread; 65 // need to make this ref-counted so it doesn't go away before we 66 // dump the record 67 StaticInstPtr staticInst; 68 TheISA::PCState pc; 69 StaticInstPtr macroStaticInst; 70 71 // The remaining fields are only valid for particular instruction 72 // types (e.g, addresses for memory ops) or when particular 73 // options are enabled (e.g., tracing full register contents). 74 // Each data field has an associated valid flag to indicate 75 // whether the data field is valid. 76 77 /*** @defgroup mem 78 * @{ 79 * Memory request information in the instruction accessed memory. 80 * @see mem_valid 81 */ 82 Addr addr; ///< The address that was accessed 83 Addr size; ///< The size of the memory request 84 unsigned flags; ///< The flags that were assigned to the request. 85 86 /** @} */ 87 88 /** @defgroup data 89 * If this instruction wrote any data values they're recorded here 90 * WARNING: Instructions are quite loose with with what they write 91 * since many instructions write multiple values (e.g. destintation 92 * register, flags, status, ...) This only captures the last write. 93 * @TODO fix this and record all destintations that an instruction writes 94 * @see data_status 95 */ 96 union { 97 uint64_t as_int; 98 double as_double; 99 } data; 100 101 /** @defgroup fetch_seq 102 * This records the serial number that the instruction was fetched in. 103 * @see fetch_seq_valid 104 */ 105 InstSeqNum fetch_seq; 106 107 /** @defgroup commit_seq 108 * This records the instruction number that was committed in the pipeline 109 * @see cp_seq_valid 110 */ 111 InstSeqNum cp_seq; 112 113 /** @ingroup data 114 * What size of data was written? 115 */
| 47#include "base/types.hh" 48#include "cpu/inst_seq.hh" 49#include "cpu/static_inst.hh" 50#include "sim/sim_object.hh" 51 52class ThreadContext; 53 54namespace Trace { 55 56class InstRecord 57{ 58 protected: 59 Tick when; 60 61 // The following fields are initialized by the constructor and 62 // thus guaranteed to be valid. 63 ThreadContext *thread; 64 // need to make this ref-counted so it doesn't go away before we 65 // dump the record 66 StaticInstPtr staticInst; 67 TheISA::PCState pc; 68 StaticInstPtr macroStaticInst; 69 70 // The remaining fields are only valid for particular instruction 71 // types (e.g, addresses for memory ops) or when particular 72 // options are enabled (e.g., tracing full register contents). 73 // Each data field has an associated valid flag to indicate 74 // whether the data field is valid. 75 76 /*** @defgroup mem 77 * @{ 78 * Memory request information in the instruction accessed memory. 79 * @see mem_valid 80 */ 81 Addr addr; ///< The address that was accessed 82 Addr size; ///< The size of the memory request 83 unsigned flags; ///< The flags that were assigned to the request. 84 85 /** @} */ 86 87 /** @defgroup data 88 * If this instruction wrote any data values they're recorded here 89 * WARNING: Instructions are quite loose with with what they write 90 * since many instructions write multiple values (e.g. destintation 91 * register, flags, status, ...) This only captures the last write. 92 * @TODO fix this and record all destintations that an instruction writes 93 * @see data_status 94 */ 95 union { 96 uint64_t as_int; 97 double as_double; 98 } data; 99 100 /** @defgroup fetch_seq 101 * This records the serial number that the instruction was fetched in. 102 * @see fetch_seq_valid 103 */ 104 InstSeqNum fetch_seq; 105 106 /** @defgroup commit_seq 107 * This records the instruction number that was committed in the pipeline 108 * @see cp_seq_valid 109 */ 110 InstSeqNum cp_seq; 111 112 /** @ingroup data 113 * What size of data was written? 114 */
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116 enum {
| 115 enum DataStatus {
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117 DataInvalid = 0, 118 DataInt8 = 1, // set to equal number of bytes 119 DataInt16 = 2, 120 DataInt32 = 4, 121 DataInt64 = 8, 122 DataDouble = 3 123 } data_status; 124 125 /** @ingroup memory 126 * Are the memory fields in the record valid? 127 */ 128 bool mem_valid; 129 130 /** @ingroup fetch_seq 131 * Are the fetch sequence number fields valid? 132 */ 133 bool fetch_seq_valid; 134 /** @ingroup commit_seq 135 * Are the commit sequence number fields valid? 136 */ 137 bool cp_seq_valid; 138 139 /** is the predicate for execution this inst true or false (not execed)? 140 */ 141 bool predicate; 142 143 public: 144 InstRecord(Tick _when, ThreadContext *_thread, 145 const StaticInstPtr _staticInst, 146 TheISA::PCState _pc, 147 const StaticInstPtr _macroStaticInst = NULL) 148 : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc), 149 macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0), 150 fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false), 151 fetch_seq_valid(false), cp_seq_valid(false), predicate(true) 152 { } 153 154 virtual ~InstRecord() { } 155 156 void setWhen(Tick new_when) { when = new_when; } 157 void setMem(Addr a, Addr s, unsigned f) 158 { 159 addr = a; size = s; flags = f; mem_valid = true; 160 } 161
| 116 DataInvalid = 0, 117 DataInt8 = 1, // set to equal number of bytes 118 DataInt16 = 2, 119 DataInt32 = 4, 120 DataInt64 = 8, 121 DataDouble = 3 122 } data_status; 123 124 /** @ingroup memory 125 * Are the memory fields in the record valid? 126 */ 127 bool mem_valid; 128 129 /** @ingroup fetch_seq 130 * Are the fetch sequence number fields valid? 131 */ 132 bool fetch_seq_valid; 133 /** @ingroup commit_seq 134 * Are the commit sequence number fields valid? 135 */ 136 bool cp_seq_valid; 137 138 /** is the predicate for execution this inst true or false (not execed)? 139 */ 140 bool predicate; 141 142 public: 143 InstRecord(Tick _when, ThreadContext *_thread, 144 const StaticInstPtr _staticInst, 145 TheISA::PCState _pc, 146 const StaticInstPtr _macroStaticInst = NULL) 147 : when(_when), thread(_thread), staticInst(_staticInst), pc(_pc), 148 macroStaticInst(_macroStaticInst), addr(0), size(0), flags(0), 149 fetch_seq(0), cp_seq(0), data_status(DataInvalid), mem_valid(false), 150 fetch_seq_valid(false), cp_seq_valid(false), predicate(true) 151 { } 152 153 virtual ~InstRecord() { } 154 155 void setWhen(Tick new_when) { when = new_when; } 156 void setMem(Addr a, Addr s, unsigned f) 157 { 158 addr = a; size = s; flags = f; mem_valid = true; 159 } 160
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162 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; } 163 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
| 161 template <typename T, size_t N> 162 void 163 setData(std::array<T, N> d) 164 { 165 data.as_int = d[0]; 166 data_status = (DataStatus)sizeof(T); 167 static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 || 168 sizeof(T) == DataInt32 || sizeof(T) == DataInt64, 169 "Type T has an unrecognized size."); 170 } 171
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164 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 165 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 166 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 167 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 168 169 void setData(int64_t d) { setData((uint64_t)d); } 170 void setData(int32_t d) { setData((uint32_t)d); } 171 void setData(int16_t d) { setData((uint16_t)d); } 172 void setData(int8_t d) { setData((uint8_t)d); } 173 174 void setData(double d) { data.as_double = d; data_status = DataDouble; } 175 176 void setFetchSeq(InstSeqNum seq) 177 { fetch_seq = seq; fetch_seq_valid = true; } 178 179 void setCPSeq(InstSeqNum seq) 180 { cp_seq = seq; cp_seq_valid = true; } 181 182 void setPredicate(bool val) { predicate = val; } 183 184 virtual void dump() = 0; 185 186 public: 187 Tick getWhen() const { return when; } 188 ThreadContext *getThread() const { return thread; } 189 StaticInstPtr getStaticInst() const { return staticInst; } 190 TheISA::PCState getPCState() const { return pc; } 191 StaticInstPtr getMacroStaticInst() const { return macroStaticInst; } 192 193 Addr getAddr() const { return addr; } 194 Addr getSize() const { return size; } 195 unsigned getFlags() const { return flags; } 196 bool getMemValid() const { return mem_valid; } 197 198 uint64_t getIntData() const { return data.as_int; } 199 double getFloatData() const { return data.as_double; } 200 int getDataStatus() const { return data_status; } 201 202 InstSeqNum getFetchSeq() const { return fetch_seq; } 203 bool getFetchSeqValid() const { return fetch_seq_valid; } 204 205 InstSeqNum getCpSeq() const { return cp_seq; } 206 bool getCpSeqValid() const { return cp_seq_valid; } 207}; 208 209class InstTracer : public SimObject 210{ 211 public: 212 InstTracer(const Params *p) : SimObject(p) 213 {} 214 215 virtual ~InstTracer() 216 {}; 217 218 virtual InstRecord * 219 getInstRecord(Tick when, ThreadContext *tc, 220 const StaticInstPtr staticInst, TheISA::PCState pc, 221 const StaticInstPtr macroStaticInst = NULL) = 0; 222}; 223 224 225 226} // namespace Trace 227 228#endif // __INSTRECORD_HH__
| 172 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; } 173 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; } 174 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; } 175 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; } 176 177 void setData(int64_t d) { setData((uint64_t)d); } 178 void setData(int32_t d) { setData((uint32_t)d); } 179 void setData(int16_t d) { setData((uint16_t)d); } 180 void setData(int8_t d) { setData((uint8_t)d); } 181 182 void setData(double d) { data.as_double = d; data_status = DataDouble; } 183 184 void setFetchSeq(InstSeqNum seq) 185 { fetch_seq = seq; fetch_seq_valid = true; } 186 187 void setCPSeq(InstSeqNum seq) 188 { cp_seq = seq; cp_seq_valid = true; } 189 190 void setPredicate(bool val) { predicate = val; } 191 192 virtual void dump() = 0; 193 194 public: 195 Tick getWhen() const { return when; } 196 ThreadContext *getThread() const { return thread; } 197 StaticInstPtr getStaticInst() const { return staticInst; } 198 TheISA::PCState getPCState() const { return pc; } 199 StaticInstPtr getMacroStaticInst() const { return macroStaticInst; } 200 201 Addr getAddr() const { return addr; } 202 Addr getSize() const { return size; } 203 unsigned getFlags() const { return flags; } 204 bool getMemValid() const { return mem_valid; } 205 206 uint64_t getIntData() const { return data.as_int; } 207 double getFloatData() const { return data.as_double; } 208 int getDataStatus() const { return data_status; } 209 210 InstSeqNum getFetchSeq() const { return fetch_seq; } 211 bool getFetchSeqValid() const { return fetch_seq_valid; } 212 213 InstSeqNum getCpSeq() const { return cp_seq; } 214 bool getCpSeqValid() const { return cp_seq_valid; } 215}; 216 217class InstTracer : public SimObject 218{ 219 public: 220 InstTracer(const Params *p) : SimObject(p) 221 {} 222 223 virtual ~InstTracer() 224 {}; 225 226 virtual InstRecord * 227 getInstRecord(Tick when, ThreadContext *tc, 228 const StaticInstPtr staticInst, TheISA::PCState pc, 229 const StaticInstPtr macroStaticInst = NULL) = 0; 230}; 231 232 233 234} // namespace Trace 235 236#endif // __INSTRECORD_HH__
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