1/*
2 * Copyright (c) 2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39 *
40 * Authors: Steve Reinhardt
41 * Nathan Binkert
42 */
43
44#ifndef __INSTRECORD_HH__
45#define __INSTRECORD_HH__
46
47#include "base/bigint.hh"
48#include "base/types.hh"
49#include "cpu/inst_seq.hh"
50#include "cpu/static_inst.hh"
51#include "sim/sim_object.hh"
52
53class ThreadContext;
54
55namespace Trace {

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108 * This records the instruction number that was committed in the pipeline
109 * @see cp_seq_valid
110 */
111 InstSeqNum cp_seq;
112
113 /** @ingroup data
114 * What size of data was written?
115 */
116 enum {
117 DataInvalid = 0,
118 DataInt8 = 1, // set to equal number of bytes
119 DataInt16 = 2,
120 DataInt32 = 4,
121 DataInt64 = 8,
122 DataDouble = 3
123 } data_status;
124

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154 virtual ~InstRecord() { }
155
156 void setWhen(Tick new_when) { when = new_when; }
157 void setMem(Addr a, Addr s, unsigned f)
158 {
159 addr = a; size = s; flags = f; mem_valid = true;
160 }
161
162 void setData(Twin64_t d) { data.as_int = d.a; data_status = DataInt64; }
163 void setData(Twin32_t d) { data.as_int = d.a; data_status = DataInt32; }
164 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
165 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
166 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
167 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
168
169 void setData(int64_t d) { setData((uint64_t)d); }
170 void setData(int32_t d) { setData((uint32_t)d); }
171 void setData(int16_t d) { setData((uint16_t)d); }

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