eventq.hh (2667:fe64b8353b1c) eventq.hh (3125:febd811bccc6)
1/*
2 * Copyright (c) 2000-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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41#include <algorithm>
42#include <map>
43#include <string>
44#include <vector>
45
46#include "sim/host.hh" // for Tick
47
48#include "base/fast_alloc.hh"
1/*
2 * Copyright (c) 2000-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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41#include <algorithm>
42#include <map>
43#include <string>
44#include <vector>
45
46#include "sim/host.hh" // for Tick
47
48#include "base/fast_alloc.hh"
49#include "base/misc.hh"
49#include "base/trace.hh"
50#include "sim/serialize.hh"
51
52class EventQueue; // forward declaration
53
54//////////////////////
55//
56// Main Event Queue

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130
131 /// Default is zero for historical reasons.
132 Default_Pri = 0,
133
134 /// CPU switches schedule the new CPU's tick event for the
135 /// same cycle (after unscheduling the old CPU's tick event).
136 /// The switch needs to come before any tick events to make
137 /// sure we don't tick both CPUs in the same cycle.
50#include "base/trace.hh"
51#include "sim/serialize.hh"
52
53class EventQueue; // forward declaration
54
55//////////////////////
56//
57// Main Event Queue

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131
132 /// Default is zero for historical reasons.
133 Default_Pri = 0,
134
135 /// CPU switches schedule the new CPU's tick event for the
136 /// same cycle (after unscheduling the old CPU's tick event).
137 /// The switch needs to come before any tick events to make
138 /// sure we don't tick both CPUs in the same cycle.
138 CPU_Switch_Pri = 31,
139 CPU_Switch_Pri = -31,
139
140 /// Serailization needs to occur before tick events also, so
141 /// that a serialize/unserialize is identical to an on-line
142 /// CPU switch.
143 Serialize_Pri = 32,
144
145 /// CPU ticks must come after other associated CPU events
146 /// (such as writebacks).

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346//////////////////////
347
348// schedule at specified time (place on event queue specified via
349// constructor)
350inline void
351Event::schedule(Tick t)
352{
353 assert(!scheduled());
140
141 /// Serailization needs to occur before tick events also, so
142 /// that a serialize/unserialize is identical to an on-line
143 /// CPU switch.
144 Serialize_Pri = 32,
145
146 /// CPU ticks must come after other associated CPU events
147 /// (such as writebacks).

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347//////////////////////
348
349// schedule at specified time (place on event queue specified via
350// constructor)
351inline void
352Event::schedule(Tick t)
353{
354 assert(!scheduled());
354 assert(t >= curTick);
355// if (t < curTick)
356// warn("t is less than curTick, ensure you don't want cycles");
355
356 setFlags(Scheduled);
357#if TRACING_ON
358 when_scheduled = curTick;
359#endif
360 _when = t;
361 queue->schedule(this);
362}

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358 setFlags(Scheduled);
359#if TRACING_ON
360 when_scheduled = curTick;
361#endif
362 _when = t;
363 queue->schedule(this);
364}

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