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> public:
> typedef int8_t Priority;
>
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< short _priority; //!< event priority
---
> Priority _priority; //!< event priority
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< enum Priority {
< /// Minimum priority
< Minimum_Pri = SHRT_MIN,
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< /// If we enable tracing on a particular cycle, do that as the
< /// very first thing so we don't miss any of the events on
< /// that cycle (even if we enter the debugger).
< Trace_Enable_Pri = -101,
---
> /// Minimum priority
> static const Priority Minimum_Pri = SCHAR_MIN;
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< /// Breakpoints should happen before anything else (except
< /// enabling trace output), so we don't miss any action when
< /// debugging.
< Debug_Break_Pri = -100,
---
> /// If we enable tracing on a particular cycle, do that as the
> /// very first thing so we don't miss any of the events on
> /// that cycle (even if we enter the debugger).
> static const Priority Trace_Enable_Pri = -101;
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< /// CPU switches schedule the new CPU's tick event for the
< /// same cycle (after unscheduling the old CPU's tick event).
< /// The switch needs to come before any tick events to make
< /// sure we don't tick both CPUs in the same cycle.
< CPU_Switch_Pri = -31,
---
> /// Breakpoints should happen before anything else (except
> /// enabling trace output), so we don't miss any action when
> /// debugging.
> static const Priority Debug_Break_Pri = -100;
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< /// For some reason "delayed" inter-cluster writebacks are
< /// scheduled before regular writebacks (which have default
< /// priority). Steve?
< Delayed_Writeback_Pri = -1,
---
> /// CPU switches schedule the new CPU's tick event for the
> /// same cycle (after unscheduling the old CPU's tick event).
> /// The switch needs to come before any tick events to make
> /// sure we don't tick both CPUs in the same cycle.
> static const Priority CPU_Switch_Pri = -31;
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< /// Default is zero for historical reasons.
< Default_Pri = 0,
---
> /// For some reason "delayed" inter-cluster writebacks are
> /// scheduled before regular writebacks (which have default
> /// priority). Steve?
> static const Priority Delayed_Writeback_Pri = -1;
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< /// Serailization needs to occur before tick events also, so
< /// that a serialize/unserialize is identical to an on-line
< /// CPU switch.
< Serialize_Pri = 32,
---
> /// Default is zero for historical reasons.
> static const Priority Default_Pri = 0;
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< /// CPU ticks must come after other associated CPU events
< /// (such as writebacks).
< CPU_Tick_Pri = 50,
---
> /// Serailization needs to occur before tick events also, so
> /// that a serialize/unserialize is identical to an on-line
> /// CPU switch.
> static const Priority Serialize_Pri = 32;
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< /// Statistics events (dump, reset, etc.) come after
< /// everything else, but before exit.
< Stat_Event_Pri = 90,
---
> /// CPU ticks must come after other associated CPU events
> /// (such as writebacks).
> static const Priority CPU_Tick_Pri = 50;
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< /// Progress events come at the end.
< Progress_Event_Pri = 95,
---
> /// Statistics events (dump, reset, etc.) come after
> /// everything else, but before exit.
> static const Priority Stat_Event_Pri = 90;
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< /// If we want to exit on this cycle, it's the very last thing
< /// we do.
< Sim_Exit_Pri = 100,
---
> /// Progress events come at the end.
> static const Priority Progress_Event_Pri = 95;
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< /// Maximum priority
< Maximum_Pri = SHRT_MAX
< };
---
> /// If we want to exit on this cycle, it's the very last thing
> /// we do.
> static const Priority Sim_Exit_Pri = 100;
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> /// Maximum priority
> static const Priority Maximum_Pri = SCHAR_MAX;
>
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< int priority() const { return _priority; }
---
> Priority priority() const { return _priority; }