eventq.hh (3125:febd811bccc6) | eventq.hh (3329:1f5c70ca9f3e) |
---|---|
1/* 2 * Copyright (c) 2000-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 106 unchanged lines hidden (view full) --- 115 116 public: 117 118 /// Event priorities, to provide tie-breakers for events scheduled 119 /// at the same cycle. Most events are scheduled at the default 120 /// priority; these values are used to control events that need to 121 /// be ordered within a cycle. 122 enum Priority { | 1/* 2 * Copyright (c) 2000-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 106 unchanged lines hidden (view full) --- 115 116 public: 117 118 /// Event priorities, to provide tie-breakers for events scheduled 119 /// at the same cycle. Most events are scheduled at the default 120 /// priority; these values are used to control events that need to 121 /// be ordered within a cycle. 122 enum Priority { |
123 /// Breakpoints should happen before anything else, so we 124 /// don't miss any action when debugging. | 123 /// If we enable tracing on a particular cycle, do that as the 124 /// very first thing so we don't miss any of the events on 125 /// that cycle (even if we enter the debugger). 126 Trace_Enable_Pri = -101, 127 128 /// Breakpoints should happen before anything else (except 129 /// enabling trace output), so we don't miss any action when 130 /// debugging. |
125 Debug_Break_Pri = -100, 126 | 131 Debug_Break_Pri = -100, 132 |
133 /// CPU switches schedule the new CPU's tick event for the 134 /// same cycle (after unscheduling the old CPU's tick event). 135 /// The switch needs to come before any tick events to make 136 /// sure we don't tick both CPUs in the same cycle. 137 CPU_Switch_Pri = -31, 138 |
|
127 /// For some reason "delayed" inter-cluster writebacks are 128 /// scheduled before regular writebacks (which have default 129 /// priority). Steve? 130 Delayed_Writeback_Pri = -1, 131 132 /// Default is zero for historical reasons. 133 Default_Pri = 0, 134 | 139 /// For some reason "delayed" inter-cluster writebacks are 140 /// scheduled before regular writebacks (which have default 141 /// priority). Steve? 142 Delayed_Writeback_Pri = -1, 143 144 /// Default is zero for historical reasons. 145 Default_Pri = 0, 146 |
135 /// CPU switches schedule the new CPU's tick event for the 136 /// same cycle (after unscheduling the old CPU's tick event). 137 /// The switch needs to come before any tick events to make 138 /// sure we don't tick both CPUs in the same cycle. 139 CPU_Switch_Pri = -31, 140 | |
141 /// Serailization needs to occur before tick events also, so 142 /// that a serialize/unserialize is identical to an on-line 143 /// CPU switch. 144 Serialize_Pri = 32, 145 146 /// CPU ticks must come after other associated CPU events 147 /// (such as writebacks). 148 CPU_Tick_Pri = 50, --- 268 unchanged lines hidden --- | 147 /// Serailization needs to occur before tick events also, so 148 /// that a serialize/unserialize is identical to an on-line 149 /// CPU switch. 150 Serialize_Pri = 32, 151 152 /// CPU ticks must come after other associated CPU events 153 /// (such as writebacks). 154 CPU_Tick_Pri = 50, --- 268 unchanged lines hidden --- |