1/*
2 * Copyright (c) 2000-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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115
116 public:
117
118 /// Event priorities, to provide tie-breakers for events scheduled
119 /// at the same cycle. Most events are scheduled at the default
120 /// priority; these values are used to control events that need to
121 /// be ordered within a cycle.
122 enum Priority {
123 /// Breakpoints should happen before anything else, so we
124 /// don't miss any action when debugging.
125 Debug_Break_Pri = -100,
126
127 /// For some reason "delayed" inter-cluster writebacks are
128 /// scheduled before regular writebacks (which have default
129 /// priority). Steve?
130 Delayed_Writeback_Pri = -1,
131
132 /// Default is zero for historical reasons.
133 Default_Pri = 0,
134
135 /// CPU switches schedule the new CPU's tick event for the
136 /// same cycle (after unscheduling the old CPU's tick event).
137 /// The switch needs to come before any tick events to make
138 /// sure we don't tick both CPUs in the same cycle.
139 CPU_Switch_Pri = -31,
140
141 /// Serailization needs to occur before tick events also, so
142 /// that a serialize/unserialize is identical to an on-line
143 /// CPU switch.
144 Serialize_Pri = 32,
145
146 /// CPU ticks must come after other associated CPU events
147 /// (such as writebacks).
148 CPU_Tick_Pri = 50,

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