1/*
2 * Copyright (c) 2000-2005 The Regents of The University of Michigan
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * Copyright (c) 2013 Mark D. Hill and David A. Wood
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are

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139 /// For some reason "delayed" inter-cluster writebacks are
140 /// scheduled before regular writebacks (which have default
141 /// priority). Steve?
142 static const Priority Delayed_Writeback_Pri = -1;
143
144 /// Default is zero for historical reasons.
145 static const Priority Default_Pri = 0;
146
147 /// Serailization needs to occur before tick events also, so
148 /// that a serialize/unserialize is identical to an on-line
149 /// CPU switch.
150 static const Priority Serialize_Pri = 32;
151
152 /// CPU ticks must come after other associated CPU events
153 /// (such as writebacks).
154 static const Priority CPU_Tick_Pri = 50;

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