clock_domain.cc (10021:9d6d630f830e) clock_domain.cc (10249:6bbb7ae309ac)
1/*
1/*
2 * Copyright (c) 2013 ARM Limited
2 * Copyright (c) 2013-2014 ARM Limited
3 * Copyright (c) 2013 Cornell University
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Vasileios Spiliopoulos
39 * Akash Bagdia
40 * Andreas Hansson
41 * Christopher Torng
3 * Copyright (c) 2013 Cornell University
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license

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34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Vasileios Spiliopoulos
39 * Akash Bagdia
40 * Andreas Hansson
41 * Christopher Torng
42 * Stephan Diestelhorst
42 */
43
43 */
44
45#include <algorithm>
46#include <functional>
47
44#include "debug/ClockDomain.hh"
45#include "params/ClockDomain.hh"
46#include "params/DerivedClockDomain.hh"
47#include "params/SrcClockDomain.hh"
48#include "sim/clock_domain.hh"
49#include "sim/voltage_domain.hh"
50#include "sim/clocked_object.hh"
51

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65
66double
67ClockDomain::voltage() const
68{
69 return _voltageDomain->voltage();
70}
71
72SrcClockDomain::SrcClockDomain(const Params *p) :
48#include "debug/ClockDomain.hh"
49#include "params/ClockDomain.hh"
50#include "params/DerivedClockDomain.hh"
51#include "params/SrcClockDomain.hh"
52#include "sim/clock_domain.hh"
53#include "sim/voltage_domain.hh"
54#include "sim/clocked_object.hh"
55

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69
70double
71ClockDomain::voltage() const
72{
73 return _voltageDomain->voltage();
74}
75
76SrcClockDomain::SrcClockDomain(const Params *p) :
73 ClockDomain(p, p->voltage_domain)
77 ClockDomain(p, p->voltage_domain),
78 freqOpPoints(p->clock),
79 _domainID(p->domain_id),
80 _perfLevel(p->init_perf_level)
74{
81{
75 clockPeriod(p->clock);
82 VoltageDomain *vdom = p->voltage_domain;
83
84 fatal_if(freqOpPoints.empty(), "DVFS: Empty set of frequencies for "\
85 "domain %d %s\n", _domainID, name());
86
87 fatal_if(!vdom, "DVFS: Empty voltage domain specified for "\
88 "domain %d %s\n", _domainID, name());
89
90 fatal_if((vdom->numVoltages() > 1) &&
91 (vdom->numVoltages() != freqOpPoints.size()),
92 "DVFS: Number of frequency and voltage scaling points do "\
93 "not match: %d:%d ID: %d %s.\n", vdom->numVoltages(),
94 freqOpPoints.size(), _domainID, name());
95
96 // Frequency (& voltage) points should be declared in descending order,
97 // NOTE: Frequency is inverted to ticks, so checking for ascending ticks
98 fatal_if(!std::is_sorted(freqOpPoints.begin(), freqOpPoints.end()),
99 "DVFS: Frequency operation points not in descending order for "\
100 "domain with ID %d\n", _domainID);
101
102 fatal_if(_perfLevel >= freqOpPoints.size(), "DVFS: Initial DVFS point %d "\
103 "is outside of list for Domain ID: %d\n", _perfLevel, _domainID);
104
105 clockPeriod(freqOpPoints[_perfLevel]);
106
107 vdom->registerSrcClockDom(this);
76}
77
78void
79SrcClockDomain::clockPeriod(Tick clock_period)
80{
81 if (clock_period == 0) {
82 fatal("%s has a clock period of zero\n", name());
83 }

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94 _clockPeriod, name());
95
96 // inform any derived clocks they need to updated their period
97 for (auto c = children.begin(); c != children.end(); ++c) {
98 (*c)->updateClockPeriod();
99 }
100}
101
108}
109
110void
111SrcClockDomain::clockPeriod(Tick clock_period)
112{
113 if (clock_period == 0) {
114 fatal("%s has a clock period of zero\n", name());
115 }

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126 _clockPeriod, name());
127
128 // inform any derived clocks they need to updated their period
129 for (auto c = children.begin(); c != children.end(); ++c) {
130 (*c)->updateClockPeriod();
131 }
132}
133
134void
135SrcClockDomain::perfLevel(PerfLevel perf_level)
136{
137 assert(validPerfLevel(perf_level));
138
139 DPRINTF(ClockDomain, "DVFS: Switching performance level of domain %s "\
140 "(id: %d) from %d to %d\n", name(), domainID(), _perfLevel,
141 perf_level);
142
143 _perfLevel = perf_level;
144
145 // Signal the voltage domain that we have changed our perf level so that the
146 // voltage domain can recompute its performance level
147 voltageDomain()->sanitiseVoltages();
148
149 // Integrated switching of the actual clock value, too
150 clockPeriod(clkPeriodAtPerfLevel());
151}
152
153void
154SrcClockDomain::serialize(std::ostream &os)
155{
156 SERIALIZE_SCALAR(_perfLevel);
157 ClockDomain::serialize(os);
158}
159
160void
161SrcClockDomain::unserialize(Checkpoint *cp, const std::string &section)
162{
163 ClockDomain::unserialize(cp, section);
164 UNSERIALIZE_SCALAR(_perfLevel);
165 perfLevel(_perfLevel);
166}
167
102SrcClockDomain *
103SrcClockDomainParams::create()
104{
105 return new SrcClockDomain(this);
106}
107
108DerivedClockDomain::DerivedClockDomain(const Params *p) :
109 ClockDomain(p, p->clk_domain->voltageDomain()),

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169SrcClockDomainParams::create()
170{
171 return new SrcClockDomain(this);
172}
173
174DerivedClockDomain::DerivedClockDomain(const Params *p) :
175 ClockDomain(p, p->clk_domain->voltageDomain()),

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