1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * Copyright (c) 2013 Cornell University
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Vasileios Spiliopoulos
39 * Akash Bagdia
40 * Andreas Hansson
41 * Christopher Torng
42 * Stephan Diestelhorst
43 */
44
45#include <algorithm>
46#include <functional>
47
48#include "debug/ClockDomain.hh"
49#include "params/ClockDomain.hh"
50#include "params/DerivedClockDomain.hh"
51#include "params/SrcClockDomain.hh"
52#include "sim/clock_domain.hh"
53#include "sim/voltage_domain.hh"
54#include "sim/clocked_object.hh"
55
56void
57ClockDomain::regStats()
58{
59 using namespace Stats;
60
61 // Expose the current clock period as a stat for observability in
62 // the dumps
63 currentClock
64 .scalar(_clockPeriod)
65 .name(params()->name + ".clock")
66 .desc("Clock period in ticks")
67 ;
68}
69
70double
71ClockDomain::voltage() const
72{
73 return _voltageDomain->voltage();
74}
75
76SrcClockDomain::SrcClockDomain(const Params *p) :
77 ClockDomain(p, p->voltage_domain),
78 freqOpPoints(p->clock),
79 _domainID(p->domain_id),
80 _perfLevel(p->init_perf_level)
81{
82 VoltageDomain *vdom = p->voltage_domain;
83
84 fatal_if(freqOpPoints.empty(), "DVFS: Empty set of frequencies for "\
85 "domain %d %s\n", _domainID, name());
86
87 fatal_if(!vdom, "DVFS: Empty voltage domain specified for "\
88 "domain %d %s\n", _domainID, name());
89
90 fatal_if((vdom->numVoltages() > 1) &&
91 (vdom->numVoltages() != freqOpPoints.size()),
92 "DVFS: Number of frequency and voltage scaling points do "\
93 "not match: %d:%d ID: %d %s.\n", vdom->numVoltages(),
94 freqOpPoints.size(), _domainID, name());
95
96 // Frequency (& voltage) points should be declared in descending order,
97 // NOTE: Frequency is inverted to ticks, so checking for ascending ticks
98 fatal_if(!std::is_sorted(freqOpPoints.begin(), freqOpPoints.end()),
99 "DVFS: Frequency operation points not in descending order for "\
100 "domain with ID %d\n", _domainID);
101
102 fatal_if(_perfLevel >= freqOpPoints.size(), "DVFS: Initial DVFS point %d "\
103 "is outside of list for Domain ID: %d\n", _perfLevel, _domainID);
104
105 clockPeriod(freqOpPoints[_perfLevel]);
106
107 vdom->registerSrcClockDom(this);
108}
109
110void
111SrcClockDomain::clockPeriod(Tick clock_period)
112{
113 if (clock_period == 0) {
114 fatal("%s has a clock period of zero\n", name());
115 }
116
117 // Align all members to the current tick
118 for (auto m = members.begin(); m != members.end(); ++m) {
119 (*m)->updateClockPeriod();
120 }
121
122 _clockPeriod = clock_period;
123
124 DPRINTF(ClockDomain,
125 "Setting clock period to %d ticks for source clock %s\n",
126 _clockPeriod, name());
127
128 // inform any derived clocks they need to updated their period
129 for (auto c = children.begin(); c != children.end(); ++c) {
130 (*c)->updateClockPeriod();
131 }
132}
133
134void
135SrcClockDomain::perfLevel(PerfLevel perf_level)
136{
137 assert(validPerfLevel(perf_level));
138
139 if (perf_level == _perfLevel) {
140 // Silently ignore identical overwrites
141 return;
142 }
143
144 DPRINTF(ClockDomain, "DVFS: Switching performance level of domain %s "\
145 "(id: %d) from %d to %d\n", name(), domainID(), _perfLevel,
146 perf_level);
147
148 _perfLevel = perf_level;
149
150 signalPerfLevelUpdate();
151}
152
153void SrcClockDomain::signalPerfLevelUpdate()
154{
155 // Signal the voltage domain that we have changed our perf level so that the
156 // voltage domain can recompute its performance level
157 voltageDomain()->sanitiseVoltages();
158
159 // Integrated switching of the actual clock value, too
160 clockPeriod(clkPeriodAtPerfLevel());
161}
162
163void
164SrcClockDomain::serialize(CheckpointOut &cp) const
165{
166 SERIALIZE_SCALAR(_perfLevel);
167 ClockDomain::serialize(cp);
168}
169
170void
171SrcClockDomain::unserialize(CheckpointIn &cp)
172{
173 ClockDomain::unserialize(cp);
174 UNSERIALIZE_SCALAR(_perfLevel);
175}
176
177void
178SrcClockDomain::startup()
179{
180 // Perform proper clock update when all related components have been
181 // created (i.e. after unserialization / object creation)
182 signalPerfLevelUpdate();
183}
184
185SrcClockDomain *
186SrcClockDomainParams::create()
187{
188 return new SrcClockDomain(this);
189}
190
191DerivedClockDomain::DerivedClockDomain(const Params *p) :
192 ClockDomain(p, p->clk_domain->voltageDomain()),
193 parent(*p->clk_domain),
194 clockDivider(p->clk_divider)
195{
196 // Ensure that clock divider setting works as frequency divider and never
197 // work as frequency multiplier
198 if (clockDivider < 1) {
199 fatal("Clock divider param cannot be less than 1");
200 }
201
202 // let the parent keep track of this derived domain so that it can
203 // propagate changes
204 parent.addDerivedDomain(this);
205
206 // update our clock period based on the parents clock
207 updateClockPeriod();
208}
209
210void
211DerivedClockDomain::updateClockPeriod()
212{
213 // Align all members to the current tick
214 for (auto m = members.begin(); m != members.end(); ++m) {
215 (*m)->updateClockPeriod();
216 }
217
218 // recalculate the clock period, relying on the fact that changes
219 // propagate downwards in the tree
220 _clockPeriod = parent.clockPeriod() * clockDivider;
221
222 DPRINTF(ClockDomain,
223 "Setting clock period to %d ticks for derived clock %s\n",
224 _clockPeriod, name());
225
226 // inform any derived clocks
227 for (auto c = children.begin(); c != children.end(); ++c) {
228 (*c)->updateClockPeriod();
229 }
230}
231
232DerivedClockDomain *
233DerivedClockDomainParams::create()
234{
235 return new DerivedClockDomain(this);
236}