1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * Copyright (c) 2013 Cornell University
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions are
17 * met: redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer;
19 * redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution;
22 * neither the name of the copyright holders nor the names of its
23 * contributors may be used to endorse or promote products derived from
24 * this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Vasileios Spiliopoulos
39 * Akash Bagdia
40 * Andreas Hansson
41 * Christopher Torng
42 * Stephan Diestelhorst
43 */
44
45#include "sim/clock_domain.hh"
46
47#include <algorithm>
48#include <functional>
49
50#include "debug/ClockDomain.hh"
51#include "params/ClockDomain.hh"
52#include "params/DerivedClockDomain.hh"
53#include "params/SrcClockDomain.hh"
54#include "sim/clocked_object.hh"
55#include "sim/voltage_domain.hh"
56
57void
58ClockDomain::regStats()
59{
60 SimObject::regStats();
61
62 using namespace Stats;
63
64 // Expose the current clock period as a stat for observability in
65 // the dumps
66 currentClock
67 .scalar(_clockPeriod)
68 .name(params()->name + ".clock")
69 .desc("Clock period in ticks")
70 ;
71}
72
73double
74ClockDomain::voltage() const
75{
76 return _voltageDomain->voltage();
77}
78
79SrcClockDomain::SrcClockDomain(const Params *p) :
80 ClockDomain(p, p->voltage_domain),
81 freqOpPoints(p->clock),
82 _domainID(p->domain_id),
83 _perfLevel(p->init_perf_level)
84{
85 VoltageDomain *vdom = p->voltage_domain;
86
87 fatal_if(freqOpPoints.empty(), "DVFS: Empty set of frequencies for "\
88 "domain %d %s\n", _domainID, name());
89
90 fatal_if(!vdom, "DVFS: Empty voltage domain specified for "\
91 "domain %d %s\n", _domainID, name());
92
93 fatal_if((vdom->numVoltages() > 1) &&
94 (vdom->numVoltages() != freqOpPoints.size()),
95 "DVFS: Number of frequency and voltage scaling points do "\
96 "not match: %d:%d ID: %d %s.\n", vdom->numVoltages(),
97 freqOpPoints.size(), _domainID, name());
98
99 // Frequency (& voltage) points should be declared in descending order,
100 // NOTE: Frequency is inverted to ticks, so checking for ascending ticks
101 fatal_if(!std::is_sorted(freqOpPoints.begin(), freqOpPoints.end()),
102 "DVFS: Frequency operation points not in descending order for "\
103 "domain with ID %d\n", _domainID);
104
105 fatal_if(_perfLevel >= freqOpPoints.size(), "DVFS: Initial DVFS point %d "\
106 "is outside of list for Domain ID: %d\n", _perfLevel, _domainID);
107
108 clockPeriod(freqOpPoints[_perfLevel]);
109
110 vdom->registerSrcClockDom(this);
111}
112
113void
114SrcClockDomain::clockPeriod(Tick clock_period)
115{
116 if (clock_period == 0) {
117 fatal("%s has a clock period of zero\n", name());
118 }
119
120 // Align all members to the current tick
121 for (auto m = members.begin(); m != members.end(); ++m) {
122 (*m)->updateClockPeriod();
123 }
124
125 _clockPeriod = clock_period;
126
127 DPRINTF(ClockDomain,
128 "Setting clock period to %d ticks for source clock %s\n",
129 _clockPeriod, name());
130
131 // inform any derived clocks they need to updated their period
132 for (auto c = children.begin(); c != children.end(); ++c) {
133 (*c)->updateClockPeriod();
134 }
135}
136
137void
138SrcClockDomain::perfLevel(PerfLevel perf_level)
139{
140 assert(validPerfLevel(perf_level));
141
142 if (perf_level == _perfLevel) {
143 // Silently ignore identical overwrites
144 return;
145 }
146
147 DPRINTF(ClockDomain, "DVFS: Switching performance level of domain %s "\
148 "(id: %d) from %d to %d\n", name(), domainID(), _perfLevel,
149 perf_level);
150
151 _perfLevel = perf_level;
152
153 signalPerfLevelUpdate();
154}
155
156void SrcClockDomain::signalPerfLevelUpdate()
157{
158 // Signal the voltage domain that we have changed our perf level so that the
159 // voltage domain can recompute its performance level
160 voltageDomain()->sanitiseVoltages();
161
162 // Integrated switching of the actual clock value, too
163 clockPeriod(clkPeriodAtPerfLevel());
164}
165
166void
167SrcClockDomain::serialize(CheckpointOut &cp) const
168{
169 SERIALIZE_SCALAR(_perfLevel);
170 ClockDomain::serialize(cp);
171}
172
173void
174SrcClockDomain::unserialize(CheckpointIn &cp)
175{
176 ClockDomain::unserialize(cp);
177 UNSERIALIZE_SCALAR(_perfLevel);
178}
179
180void
181SrcClockDomain::startup()
182{
183 // Perform proper clock update when all related components have been
184 // created (i.e. after unserialization / object creation)
185 signalPerfLevelUpdate();
186}
187
188SrcClockDomain *
189SrcClockDomainParams::create()
190{
191 return new SrcClockDomain(this);
192}
193
194DerivedClockDomain::DerivedClockDomain(const Params *p) :
195 ClockDomain(p, p->clk_domain->voltageDomain()),
196 parent(*p->clk_domain),
197 clockDivider(p->clk_divider)
198{
199 // Ensure that clock divider setting works as frequency divider and never
200 // work as frequency multiplier
201 if (clockDivider < 1) {
202 fatal("Clock divider param cannot be less than 1");
203 }
204
205 // let the parent keep track of this derived domain so that it can
206 // propagate changes
207 parent.addDerivedDomain(this);
208
209 // update our clock period based on the parents clock
210 updateClockPeriod();
211}
212
213void
214DerivedClockDomain::updateClockPeriod()
215{
216 // Align all members to the current tick
217 for (auto m = members.begin(); m != members.end(); ++m) {
218 (*m)->updateClockPeriod();
219 }
220
221 // recalculate the clock period, relying on the fact that changes
222 // propagate downwards in the tree
223 _clockPeriod = parent.clockPeriod() * clockDivider;
224
225 DPRINTF(ClockDomain,
226 "Setting clock period to %d ticks for derived clock %s\n",
227 _clockPeriod, name());
228
229 // inform any derived clocks
230 for (auto c = children.begin(); c != children.end(); ++c) {
231 (*c)->updateClockPeriod();
232 }
233}
234
235DerivedClockDomain *
236DerivedClockDomainParams::create()
237{
238 return new DerivedClockDomain(this);
239}