1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Nathan Binkert
29# Rick Strong
30
31from m5.SimObject import SimObject
32from m5.defines import buildEnv
33from m5.params import *
34from m5.proxy import *
35
36from DVFSHandler import *
37from SimpleMemory import *
38
39class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
40 'atomic_noncaching']
41
42class System(MemObject):
43 type = 'System'
44 cxx_header = "sim/system.hh"
45 system_port = MasterPort("System port")
46
47 @classmethod
48 def export_method_cxx_predecls(cls, code):
49 code('#include "sim/system.hh"')
50
51 @classmethod
52 def export_methods(cls, code):
53 code('''
54 Enums::MemoryMode getMemoryMode() const;
55 void setMemoryMode(Enums::MemoryMode mode);
56''')
57
58 memories = VectorParam.AbstractMemory(Self.all,
59 "All memories in the system")
60 mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
61
| 1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Nathan Binkert
29# Rick Strong
30
31from m5.SimObject import SimObject
32from m5.defines import buildEnv
33from m5.params import *
34from m5.proxy import *
35
36from DVFSHandler import *
37from SimpleMemory import *
38
39class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
40 'atomic_noncaching']
41
42class System(MemObject):
43 type = 'System'
44 cxx_header = "sim/system.hh"
45 system_port = MasterPort("System port")
46
47 @classmethod
48 def export_method_cxx_predecls(cls, code):
49 code('#include "sim/system.hh"')
50
51 @classmethod
52 def export_methods(cls, code):
53 code('''
54 Enums::MemoryMode getMemoryMode() const;
55 void setMemoryMode(Enums::MemoryMode mode);
56''')
57
58 memories = VectorParam.AbstractMemory(Self.all,
59 "All memories in the system")
60 mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
61
|
| 62 thermal_model = Param.ThermalModel(NULL, "Thermal model")
63 thermal_components = VectorParam.SimObject([],
64 "A collection of all thermal components in the system.")
65
|
62 # When reserving memory on the host, we have the option of
63 # reserving swap space or not (by passing MAP_NORESERVE to
64 # mmap). By enabling this flag, we accomodate cases where a large
65 # (but sparse) memory is simulated.
66 mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \
67 "without reserving swap")
68
69 # The memory ranges are to be populated when creating the system
70 # such that these can be passed from the I/O subsystem through an
71 # I/O bridge or cache
72 mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory")
73
74 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
75
76 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when "
77 "encountering work item annotations.")
78 work_item_id = Param.Int(-1, "specific work item id")
79 num_work_ids = Param.Int(16, "Number of distinct work item types")
80 work_begin_cpu_id_exit = Param.Int(-1,
81 "work started on specific id, now exit simulation")
82 work_begin_ckpt_count = Param.Counter(0,
83 "create checkpoint when work items begin count value is reached")
84 work_begin_exit_count = Param.Counter(0,
85 "exit simulation when work items begin count value is reached")
86 work_end_ckpt_count = Param.Counter(0,
87 "create checkpoint when work items end count value is reached")
88 work_end_exit_count = Param.Counter(0,
89 "exit simulation when work items end count value is reached")
90 work_cpus_ckpt_count = Param.Counter(0,
91 "create checkpoint when active cpu count value is reached")
92
93 init_param = Param.UInt64(0, "numerical value to pass into simulator")
94 boot_osflags = Param.String("a", "boot flags to pass to the kernel")
95 kernel = Param.String("", "file that contains the kernel code")
96 kernel_addr_check = Param.Bool(True,
97 "whether to address check on kernel (disable for baremetal)")
98 readfile = Param.String("", "file to read startup script from")
99 symbolfile = Param.String("", "file to get the symbols from")
100 load_addr_mask = Param.UInt64(0xffffffffff,
101 "Address to mask loading binaries with")
102 load_offset = Param.UInt64(0, "Address to offset loading binaries with")
103
104 multi_thread = Param.Bool(False,
105 "Supports multi-threaded CPUs? Impacts Thread/Context IDs")
106
107 # Dynamic voltage and frequency handler for the system, disabled by default
108 # Provide list of domains that need to be controlled by the handler
109 dvfs_handler = DVFSHandler()
| 66 # When reserving memory on the host, we have the option of
67 # reserving swap space or not (by passing MAP_NORESERVE to
68 # mmap). By enabling this flag, we accomodate cases where a large
69 # (but sparse) memory is simulated.
70 mmap_using_noreserve = Param.Bool(False, "mmap the backing store " \
71 "without reserving swap")
72
73 # The memory ranges are to be populated when creating the system
74 # such that these can be passed from the I/O subsystem through an
75 # I/O bridge or cache
76 mem_ranges = VectorParam.AddrRange([], "Ranges that constitute main memory")
77
78 cache_line_size = Param.Unsigned(64, "Cache line size in bytes")
79
80 exit_on_work_items = Param.Bool(False, "Exit from the simulation loop when "
81 "encountering work item annotations.")
82 work_item_id = Param.Int(-1, "specific work item id")
83 num_work_ids = Param.Int(16, "Number of distinct work item types")
84 work_begin_cpu_id_exit = Param.Int(-1,
85 "work started on specific id, now exit simulation")
86 work_begin_ckpt_count = Param.Counter(0,
87 "create checkpoint when work items begin count value is reached")
88 work_begin_exit_count = Param.Counter(0,
89 "exit simulation when work items begin count value is reached")
90 work_end_ckpt_count = Param.Counter(0,
91 "create checkpoint when work items end count value is reached")
92 work_end_exit_count = Param.Counter(0,
93 "exit simulation when work items end count value is reached")
94 work_cpus_ckpt_count = Param.Counter(0,
95 "create checkpoint when active cpu count value is reached")
96
97 init_param = Param.UInt64(0, "numerical value to pass into simulator")
98 boot_osflags = Param.String("a", "boot flags to pass to the kernel")
99 kernel = Param.String("", "file that contains the kernel code")
100 kernel_addr_check = Param.Bool(True,
101 "whether to address check on kernel (disable for baremetal)")
102 readfile = Param.String("", "file to read startup script from")
103 symbolfile = Param.String("", "file to get the symbols from")
104 load_addr_mask = Param.UInt64(0xffffffffff,
105 "Address to mask loading binaries with")
106 load_offset = Param.UInt64(0, "Address to offset loading binaries with")
107
108 multi_thread = Param.Bool(False,
109 "Supports multi-threaded CPUs? Impacts Thread/Context IDs")
110
111 # Dynamic voltage and frequency handler for the system, disabled by default
112 # Provide list of domains that need to be controlled by the handler
113 dvfs_handler = DVFSHandler()
|