ClockedObject.py (11430:bd1c6789c33f) | ClockedObject.py (11524:3101ce98c55c) |
---|---|
1# Copyright (c) 2012 ARM Limited | 1# Copyright (c) 2012, 2015-2016 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 24 unchanged lines hidden (view full) --- 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37 38from m5.SimObject import SimObject 39from m5.params import * 40from m5.proxy import * 41 | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 24 unchanged lines hidden (view full) --- 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37 38from m5.SimObject import SimObject 39from m5.params import * 40from m5.proxy import * 41 |
42# Enumerate set of allowed power states that can be used by a clocked object. 43# The list is kept generic to express a base minimal set. 44# State definition :- 45# Undefined: Invalid state, no power state derived information is available. 46# On: The logic block is actively running and consuming dynamic and leakage 47# energy depending on the amount of processing required. 48# Clk_gated: The clock circuity within the block is gated to save dynamic 49# energy, the power supply to the block is still on and leakage 50# energy is being consumed by the block. 51# Sram_retention: The SRAMs within the logic blocks are pulled into retention 52# state to reduce leakage energy further. 53# Off: The logic block is power gated and is not consuming any energy. 54class PwrState(Enum): vals = ['UNDEFINED', 55 'ON', 56 'CLK_GATED', 57 'SRAM_RETENTION', 58 'OFF'] 59 |
|
42class ClockedObject(SimObject): 43 type = 'ClockedObject' 44 abstract = True 45 cxx_header = "sim/clocked_object.hh" 46 47 # The clock domain this clocked object belongs to, inheriting the 48 # parent's clock domain by default 49 clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain") | 60class ClockedObject(SimObject): 61 type = 'ClockedObject' 62 abstract = True 63 cxx_header = "sim/clocked_object.hh" 64 65 # The clock domain this clocked object belongs to, inheriting the 66 # parent's clock domain by default 67 clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain") |
68 69 # Provide initial power state, should ideally get redefined in startup 70 # routine 71 default_p_state = Param.PwrState("UNDEFINED", "Default Power State") 72 73 p_state_clk_gate_min = Param.Latency('1ns',"Min value of the distribution") 74 p_state_clk_gate_max = Param.Latency('1s',"Max value of the distribution") 75 p_state_clk_gate_bins = Param.Unsigned('20', 76 "# bins in clk gated distribution") |
|