dot_writer.py (9854:e4a4cdfb1b81) dot_writer.py (10176:266db8ff9ae8)
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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53# recursivly, traversing all children of the given root.
54#
55# pydot is required. When missing, no output will be generated.
56#
57#####################################################################
58
59import m5, os, re
60from m5.SimObject import isRoot, isSimObjectVector
1# Copyright (c) 2012-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 44 unchanged lines hidden (view full) ---

53# recursivly, traversing all children of the given root.
54#
55# pydot is required. When missing, no output will be generated.
56#
57#####################################################################
58
59import m5, os, re
60from m5.SimObject import isRoot, isSimObjectVector
61from m5.params import PortRef
61from m5.util import warn
62try:
63 import pydot
64except:
65 pydot = False
66
67# need to create all nodes (components) before creating edges (memory channels)
68def dot_create_nodes(simNode, callgraph):

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101def dot_create_edges(simNode, callgraph):
102 for port_name in simNode._ports.keys():
103 port = simNode._port_refs.get(port_name, None)
104 if port != None:
105 full_path = re.sub('\.', '_', simNode.path())
106 full_port_name = full_path + "_" + port_name
107 port_node = dot_create_node(simNode, full_port_name, port_name)
108 # create edges
62from m5.util import warn
63try:
64 import pydot
65except:
66 pydot = False
67
68# need to create all nodes (components) before creating edges (memory channels)
69def dot_create_nodes(simNode, callgraph):

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102def dot_create_edges(simNode, callgraph):
103 for port_name in simNode._ports.keys():
104 port = simNode._port_refs.get(port_name, None)
105 if port != None:
106 full_path = re.sub('\.', '_', simNode.path())
107 full_port_name = full_path + "_" + port_name
108 port_node = dot_create_node(simNode, full_port_name, port_name)
109 # create edges
109 if type(port) is m5.params.PortRef:
110 if isinstance(port, PortRef):
110 dot_add_edge(simNode, callgraph, full_port_name, port)
111 else:
112 for p in port.elements:
113 dot_add_edge(simNode, callgraph, full_port_name, p)
114
115 # recurse to children
116 if simNode._children:
117 for c in simNode._children:

--- 159 unchanged lines hidden --- 		111 dot_add_edge(simNode, callgraph, full_port_name, port)
112 else:
113 for p in port.elements:
114 dot_add_edge(simNode, callgraph, full_port_name, p)
115
116 # recurse to children
117 if simNode._children:
118 for c in simNode._children:

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