1# Copyright (c) 2012-2013,2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 103 unchanged lines hidden (view full) --- 112 for port_name in simNode._ports.keys(): 113 port = simNode._port_refs.get(port_name, None) 114 if port != None: 115 full_path = re.sub('\.', '_', simNode.path()) 116 full_port_name = full_path + "_" + port_name 117 port_node = dot_create_node(simNode, full_port_name, port_name) 118 # create edges 119 if isinstance(port, PortRef): |
120 if port.peer: 121 dot_add_edge(simNode, callgraph, full_port_name, port) |
122 else: 123 for p in port.elements: |
124 if p.peer: 125 dot_add_edge(simNode, callgraph, full_port_name, p) |
126 127 # recurse to children 128 for child in simnode_children(simNode): 129 dot_create_edges(child, callgraph) 130 131def dot_add_edge(simNode, callgraph, full_port_name, port): 132 peer = port.peer 133 full_peer_path = re.sub('\.', '_', peer.simobj.path()) --- 252 unchanged lines hidden --- |