params.py (3105:993f1abefd67) params.py (3109:c3956807347f)
1# Copyright (c) 2004-2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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771 if attr == 'peerObj':
772 # shorthand for proxies
773 return self.peer.simobj
774 raise AttributeError, "'%s' object has no attribute '%s'" % \
775 (self.__class__.__name__, attr)
776
777 # Full connection is symmetric (both ways). Called via
778 # SimObject.__setattr__ as a result of a port assignment, e.g.,
1# Copyright (c) 2004-2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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771 if attr == 'peerObj':
772 # shorthand for proxies
773 return self.peer.simobj
774 raise AttributeError, "'%s' object has no attribute '%s'" % \
775 (self.__class__.__name__, attr)
776
777 # Full connection is symmetric (both ways). Called via
778 # SimObject.__setattr__ as a result of a port assignment, e.g.,
779 # "obj1.portA = obj2.portB", or via VectorPortRef.__setitem__,
779 # "obj1.portA = obj2.portB", or via VectorPortElementRef.__setitem__,
780 # e.g., "obj1.portA[3] = obj2.portB".
781 def connect(self, other):
782 if isinstance(other, VectorPortRef):
783 # reference to plain VectorPort is implicit append
784 other = other._get_next()
780 # e.g., "obj1.portA[3] = obj2.portB".
781 def connect(self, other):
782 if isinstance(other, VectorPortRef):
783 # reference to plain VectorPort is implicit append
784 other = other._get_next()
785 if not (isinstance(other, PortRef) or proxy.isproxy(other)):
786 raise TypeError, \
787 "assigning non-port reference '%s' to port '%s'" \
788 % (other, self)
789 if self.peer and not proxy.isproxy(self.peer):
790 print "warning: overwriting port", self, \
791 "value", self.peer, "with", other
792 self.peer = other
785 if self.peer and not proxy.isproxy(self.peer):
786 print "warning: overwriting port", self, \
787 "value", self.peer, "with", other
788 self.peer = other
793 assert(not isinstance(self.peer, VectorPortRef))
794 if isinstance(other, PortRef) and other.peer is not self:
795 other.connect(self)
789 if proxy.isproxy(other):
790 other.set_param_desc(PortParamDesc())
791 elif isinstance(other, PortRef):
792 if other.peer is not self:
793 other.connect(self)
794 else:
795 raise TypeError, \
796 "assigning non-port reference '%s' to port '%s'" \
797 % (other, self)
796
797 def clone(self, simobj, memo):
798 if memo.has_key(self):
799 return memo[self]
800 newRef = copy.copy(self)
801 memo[self] = newRef
802 newRef.simobj = simobj
803 assert(isSimObject(newRef.simobj))

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842# Can be indexed to retrieve individual VectorPortElementRef instances.
843class VectorPortRef(object):
844 def __init__(self, simobj, name):
845 assert(isSimObject(simobj) or isSimObjectClass(simobj))
846 self.simobj = simobj
847 self.name = name
848 self.elements = []
849
798
799 def clone(self, simobj, memo):
800 if memo.has_key(self):
801 return memo[self]
802 newRef = copy.copy(self)
803 memo[self] = newRef
804 newRef.simobj = simobj
805 assert(isSimObject(newRef.simobj))

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844# Can be indexed to retrieve individual VectorPortElementRef instances.
845class VectorPortRef(object):
846 def __init__(self, simobj, name):
847 assert(isSimObject(simobj) or isSimObjectClass(simobj))
848 self.simobj = simobj
849 self.name = name
850 self.elements = []
851
852 def __str__(self):
853 return '%s.%s[:]' % (self.simobj, self.name)
854
850 # for config.ini, print peer's name (not ours)
851 def ini_str(self):
852 return ' '.join([el.ini_str() for el in self.elements])
853
854 def __getitem__(self, key):
855 if not isinstance(key, int):
856 raise TypeError, "VectorPort index must be integer"
857 if key >= len(self.elements):

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865 return self[len(self.elements)]
866
867 def __setitem__(self, key, value):
868 if not isinstance(key, int):
869 raise TypeError, "VectorPort index must be integer"
870 self[key].connect(value)
871
872 def connect(self, other):
855 # for config.ini, print peer's name (not ours)
856 def ini_str(self):
857 return ' '.join([el.ini_str() for el in self.elements])
858
859 def __getitem__(self, key):
860 if not isinstance(key, int):
861 raise TypeError, "VectorPort index must be integer"
862 if key >= len(self.elements):

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870 return self[len(self.elements)]
871
872 def __setitem__(self, key, value):
873 if not isinstance(key, int):
874 raise TypeError, "VectorPort index must be integer"
875 self[key].connect(value)
876
877 def connect(self, other):
873 # reference to plain VectorPort is implicit append
874 self._get_next().connect(other)
878 if isinstance(other, (list, tuple)):
879 # Assign list of port refs to vector port.
880 # For now, append them... not sure if that's the right semantics
881 # or if it should replace the current vector.
882 for ref in other:
883 self._get_next().connect(ref)
884 else:
885 # scalar assignment to plain VectorPort is implicit append
886 self._get_next().connect(other)
875
887
888 def clone(self, simobj, memo):
889 if memo.has_key(self):
890 return memo[self]
891 newRef = copy.copy(self)
892 memo[self] = newRef
893 newRef.simobj = simobj
894 assert(isSimObject(newRef.simobj))
895 newRef.elements = [el.clone(simobj, memo) for el in self.elements]
896 return newRef
897
876 def unproxy(self, simobj):
877 [el.unproxy(simobj) for el in self.elements]
878
879 def ccConnect(self):
880 [el.ccConnect() for el in self.elements]
881
882# Port description object. Like a ParamDesc object, this represents a
883# logical port in the SimObject class, not a particular port on a

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910class VectorPort(Port):
911 def __init__(self, *args):
912 Port.__init__(self, *args)
913 self.isVec = True
914
915 def makeRef(self, simobj):
916 return VectorPortRef(simobj, self.name)
917
898 def unproxy(self, simobj):
899 [el.unproxy(simobj) for el in self.elements]
900
901 def ccConnect(self):
902 [el.ccConnect() for el in self.elements]
903
904# Port description object. Like a ParamDesc object, this represents a
905# logical port in the SimObject class, not a particular port on a

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932class VectorPort(Port):
933 def __init__(self, *args):
934 Port.__init__(self, *args)
935 self.isVec = True
936
937 def makeRef(self, simobj):
938 return VectorPortRef(simobj, self.name)
939
940# 'Fake' ParamDesc for Port references to assign to the _pdesc slot of
941# proxy objects (via set_param_desc()) so that proxy error messages
942# make sense.
943class PortParamDesc(object):
944 __metaclass__ = Singleton
918
945
946 ptype_str = 'Port'
947 ptype = Port
919
948
949
920__all__ = ['Param', 'VectorParam',
921 'Enum', 'Bool', 'String', 'Float',
922 'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
923 'Int32', 'UInt32', 'Int64', 'UInt64',
924 'Counter', 'Addr', 'Tick', 'Percent',
925 'TcpPort', 'UdpPort', 'EthernetAddr',
926 'MemorySize', 'MemorySize32',
927 'Latency', 'Frequency', 'RootClock', 'Clock',
928 'NetworkBandwidth', 'MemoryBandwidth',
929 'Range', 'AddrRange', 'TickRange',
930 'MaxAddr', 'MaxTick', 'AllMemory',
931 'NextEthernetAddr', 'NULL',
932 'Port', 'VectorPort']
933
934# see comment on imports at end of __init__.py.
935from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
936import proxy
937import objects
938import cc_main
950__all__ = ['Param', 'VectorParam',
951 'Enum', 'Bool', 'String', 'Float',
952 'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
953 'Int32', 'UInt32', 'Int64', 'UInt64',
954 'Counter', 'Addr', 'Tick', 'Percent',
955 'TcpPort', 'UdpPort', 'EthernetAddr',
956 'MemorySize', 'MemorySize32',
957 'Latency', 'Frequency', 'RootClock', 'Clock',
958 'NetworkBandwidth', 'MemoryBandwidth',
959 'Range', 'AddrRange', 'TickRange',
960 'MaxAddr', 'MaxTick', 'AllMemory',
961 'NextEthernetAddr', 'NULL',
962 'Port', 'VectorPort']
963
964# see comment on imports at end of __init__.py.
965from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
966import proxy
967import objects
968import cc_main