| params.py (13871:ab1644706e11) | params.py (13890:564dee39e58e) |
|---|---|
| 1# Copyright (c) 2012-2014, 2017, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 2085 unchanged lines hidden (view full) --- 2094 cls.cxx_predecls(self, code) 2095 2096 # Declare an unsigned int with the same name as the port, that 2097 # will eventually hold the number of connected ports (and thus the 2098 # number of elements for a VectorPort). 2099 def cxx_decl(self, code): 2100 code('unsigned int port_${{self.name}}_connection_count;') 2101 | 1# Copyright (c) 2012-2014, 2017, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 2085 unchanged lines hidden (view full) --- 2094 cls.cxx_predecls(self, code) 2095 2096 # Declare an unsigned int with the same name as the port, that 2097 # will eventually hold the number of connected ports (and thus the 2098 # number of elements for a VectorPort). 2099 def cxx_decl(self, code): 2100 code('unsigned int port_${{self.name}}_connection_count;') 2101 |
| 2102Port.compat('MASTER', 'SLAVE') | 2102Port.compat('GEM5 REQUESTER', 'GEM5 RESPONDER') |
| 2103 | 2103 |
| 2104class MasterPort(Port): 2105 # MasterPort("description") | 2104class RequestPort(Port): 2105 # RequestPort("description") |
| 2106 def __init__(self, desc): | 2106 def __init__(self, desc): |
| 2107 super(MasterPort, self).__init__('MASTER', desc, is_source=True) | 2107 super(RequestPort, self).__init__( 2108 'GEM5 REQUESTER', desc, is_source=True) |
| 2108 | 2109 |
| 2109class SlavePort(Port): 2110 # SlavePort("description") | 2110class ResponsePort(Port): 2111 # ResponsePort("description") |
| 2111 def __init__(self, desc): | 2112 def __init__(self, desc): |
| 2112 super(SlavePort, self).__init__('SLAVE', desc) | 2113 super(ResponsePort, self).__init__('GEM5 RESPONDER', desc) |
| 2113 2114# VectorPort description object. Like Port, but represents a vector 2115# of connections (e.g., as on a XBar). 2116class VectorPort(Port): 2117 # VectorPort("role", "description") 2118 def __init__(self, role, desc, is_source=False): 2119 super(VectorPort, self).__init__(role, desc, is_source) 2120 self.isVec = True 2121 2122 def makeRef(self, simobj): 2123 return VectorPortRef(simobj, self.name, self.role, self.is_source) 2124 | 2114 2115# VectorPort description object. Like Port, but represents a vector 2116# of connections (e.g., as on a XBar). 2117class VectorPort(Port): 2118 # VectorPort("role", "description") 2119 def __init__(self, role, desc, is_source=False): 2120 super(VectorPort, self).__init__(role, desc, is_source) 2121 self.isVec = True 2122 2123 def makeRef(self, simobj): 2124 return VectorPortRef(simobj, self.name, self.role, self.is_source) 2125 |
| 2125class VectorMasterPort(VectorPort): 2126 # VectorMasterPort("description") | 2126class VectorRequestPort(VectorPort): 2127 # VectorRequestPort("description") |
| 2127 def __init__(self, desc): | 2128 def __init__(self, desc): |
| 2128 super(VectorMasterPort, self).__init__('MASTER', desc, is_source=True) | 2129 super(VectorRequestPort, self).__init__( 2130 'GEM5 REQUESTER', desc, is_source=True) |
| 2129 | 2131 |
| 2130class VectorSlavePort(VectorPort): 2131 # VectorSlavePort("description") | 2132class VectorResponsePort(VectorPort): 2133 # VectorResponsePort("description") |
| 2132 def __init__(self, desc): | 2134 def __init__(self, desc): |
| 2133 super(VectorSlavePort, self).__init__('SLAVE', desc) | 2135 super(VectorResponsePort, self).__init__('GEM5 RESPONDER', desc) |
| 2134 | 2136 |
| 2137# Old names, maintained for compatibility. 2138MasterPort = RequestPort 2139SlavePort = ResponsePort 2140VectorMasterPort = VectorRequestPort 2141VectorSlavePort = VectorResponsePort 2142 |
|
| 2135# 'Fake' ParamDesc for Port references to assign to the _pdesc slot of 2136# proxy objects (via set_param_desc()) so that proxy error messages 2137# make sense. 2138class PortParamDesc(object): 2139 __metaclass__ = Singleton 2140 2141 ptype_str = 'Port' 2142 ptype = Port --- 16 unchanged lines hidden (view full) --- 2159 'IpAddress', 'IpNetmask', 'IpWithPort', 2160 'MemorySize', 'MemorySize32', 2161 'Latency', 'Frequency', 'Clock', 'Voltage', 'Current', 'Energy', 2162 'NetworkBandwidth', 'MemoryBandwidth', 2163 'AddrRange', 2164 'MaxAddr', 'MaxTick', 'AllMemory', 2165 'Time', 2166 'NextEthernetAddr', 'NULL', | 2143# 'Fake' ParamDesc for Port references to assign to the _pdesc slot of 2144# proxy objects (via set_param_desc()) so that proxy error messages 2145# make sense. 2146class PortParamDesc(object): 2147 __metaclass__ = Singleton 2148 2149 ptype_str = 'Port' 2150 ptype = Port --- 16 unchanged lines hidden (view full) --- 2167 'IpAddress', 'IpNetmask', 'IpWithPort', 2168 'MemorySize', 'MemorySize32', 2169 'Latency', 'Frequency', 'Clock', 'Voltage', 'Current', 'Energy', 2170 'NetworkBandwidth', 'MemoryBandwidth', 2171 'AddrRange', 2172 'MaxAddr', 'MaxTick', 'AllMemory', 2173 'Time', 2174 'NextEthernetAddr', 'NULL', |
| 2167 'Port', 'MasterPort', 'SlavePort', 2168 'VectorPort', 'VectorMasterPort', 'VectorSlavePort'] | 2175 'Port', 'RequestPort', 'ResponsePort', 'MasterPort', 'SlavePort', 2176 'VectorPort', 'VectorRequestPort', 'VectorResponsePort', 2177 'VectorMasterPort', 'VectorSlavePort'] |