| params.py (13711:e796a82c5154) | params.py (13714:35636064b7a1) |
|---|---|
| 1# Copyright (c) 2012-2014, 2017, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 54 unchanged lines hidden (view full) --- 63 64import copy 65import datetime 66import re 67import sys 68import time 69import math 70 | 1# Copyright (c) 2012-2014, 2017, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 54 unchanged lines hidden (view full) --- 63 64import copy 65import datetime 66import re 67import sys 68import time 69import math 70 |
| 71import proxy 72import ticks 73from util import * | 71from . import proxy 72from . import ticks 73from .util import * |
| 74 75def isSimObject(*args, **kwargs): 76 return SimObject.isSimObject(*args, **kwargs) 77 78def isSimObjectSequence(*args, **kwargs): 79 return SimObject.isSimObjectSequence(*args, **kwargs) 80 81def isSimObjectClass(*args, **kwargs): --- 2072 unchanged lines hidden (view full) --- 2154 'NetworkBandwidth', 'MemoryBandwidth', 2155 'AddrRange', 2156 'MaxAddr', 'MaxTick', 'AllMemory', 2157 'Time', 2158 'NextEthernetAddr', 'NULL', 2159 'MasterPort', 'SlavePort', 2160 'VectorMasterPort', 'VectorSlavePort'] 2161 | 74 75def isSimObject(*args, **kwargs): 76 return SimObject.isSimObject(*args, **kwargs) 77 78def isSimObjectSequence(*args, **kwargs): 79 return SimObject.isSimObjectSequence(*args, **kwargs) 80 81def isSimObjectClass(*args, **kwargs): --- 2072 unchanged lines hidden (view full) --- 2154 'NetworkBandwidth', 'MemoryBandwidth', 2155 'AddrRange', 2156 'MaxAddr', 'MaxTick', 'AllMemory', 2157 'Time', 2158 'NextEthernetAddr', 'NULL', 2159 'MasterPort', 'SlavePort', 2160 'VectorMasterPort', 'VectorSlavePort'] 2161 |
| 2162import SimObject | 2162from . import SimObject |