1# Copyright (c) 2012-2014 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 372 unchanged lines hidden (view full) --- 381 382 def swig_module_name(self): 383 return "%s_vector" % self.ptype_str 384 385 def swig_predecls(self, code): 386 code('%import "${{self.swig_module_name()}}.i"') 387 388 def swig_decl(self, code): |
389 code('%module(package="_m5") ${{self.swig_module_name()}}') |
390 code('%{') 391 self.ptype.cxx_predecls(code) 392 code('%}') 393 code() 394 # Make sure the SWIGPY_SLICE_ARG is defined through this inclusion 395 code('%include "std_container.i"') 396 code() 397 self.ptype.swig_predecls(code) --- 216 unchanged lines hidden (view full) --- 614class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 615 616class Cycles(CheckedInt): 617 cxx_type = 'Cycles' 618 size = 64 619 unsigned = True 620 621 def getValue(self): |
622 from _m5.core import Cycles |
623 return Cycles(self.value) 624 625 @classmethod 626 def cxx_ini_predecls(cls, code): 627 # Assume that base/str.hh will be included anyway 628 # code('#include "base/str.hh"') 629 pass 630 --- 192 unchanged lines hidden (view full) --- 823 code('if (_ret)') 824 code(' ${dest} = AddrRange(_start, _end, _intlvHighBit, \ 825 _xorHighBit, _intlvBits, _intlvMatch);') 826 code('${ret} _ret;') 827 828 def getValue(self): 829 # Go from the Python class to the wrapped C++ class generated 830 # by swig |
831 from _m5.range import AddrRange |
832 833 return AddrRange(long(self.start), long(self.end), 834 int(self.intlvHighBit), int(self.xorHighBit), 835 int(self.intlvBits), int(self.intlvMatch)) 836 837# Boolean parameter type. Python doesn't let you subclass bool, since 838# it doesn't want to let you create multiple instances of True and 839# False. Thus this is a little more complicated than String. --- 533 unchanged lines hidden (view full) --- 1373 1374 if not cls.wrapper_is_struct: 1375 code('} // namespace $wrapper_name') 1376 code.dedent(1) 1377 1378 def swig_decl(cls, code): 1379 name = cls.__name__ 1380 code('''\ |
1381%module(package="_m5") enum_$name |
1382 1383%{ 1384#include "enums/$name.hh" 1385%} 1386 1387%include "enums/$name.hh" 1388''') 1389 --- 24 unchanged lines hidden (view full) --- 1414 return value 1415 1416 @classmethod 1417 def cxx_predecls(cls, code): 1418 code('#include "enums/$0.hh"', cls.__name__) 1419 1420 @classmethod 1421 def swig_predecls(cls, code): |
1422 code('%import "python/_m5/enum_$0.i"', cls.__name__) |
1423 1424 @classmethod 1425 def cxx_ini_parse(cls, code, src, dest, ret): 1426 code('if (false) {') 1427 for elem_name in cls.map.iterkeys(): 1428 code('} else if (%s == "%s") {' % (src, elem_name)) 1429 code.indent() 1430 code('%s = Enums::%s;' % (dest, elem_name)) --- 473 unchanged lines hidden (view full) --- 1904 except: 1905 print "Error in unproxying port '%s' of %s" % \ 1906 (self.name, self.simobj.path()) 1907 raise 1908 self.connect(realPeer) 1909 1910 # Call C++ to create corresponding port connection between C++ objects 1911 def ccConnect(self): |
1912 from _m5.pyobject import connectPorts |
1913 1914 if self.role == 'SLAVE': 1915 # do nothing and let the master take care of it 1916 return 1917 1918 if self.ccConnected: # already done this 1919 return 1920 peer = self.peer --- 211 unchanged lines hidden --- |