1# Copyright (c) 2004-2006 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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747#
748# Ports are used to interconnect objects in the memory system.
749#
750#####################################################################
751
752# Port reference: encapsulates a reference to a particular port on a
753# particular SimObject.
754class PortRef(object):
755 def __init__(self, simobj, name, isVec):
756 assert(isSimObject(simobj))
757 self.simobj = simobj
758 self.name = name
759 self.index = -1
760 self.isVec = isVec # is this a vector port?
761 self.peer = None # not associated with another port yet
762 self.ccConnected = False # C++ port connection done?
763
764 def __str__(self):
765 ext = ''
766 if self.isVec:
767 ext = '[%d]' % self.index
768 return '%s.%s%s' % (self.simobj.path(), self.name, ext)
769
770 # Set peer port reference. Called via __setattr__ as a result of
771 # a port assignment, e.g., "obj1.port1 = obj2.port2".
772 def setPeer(self, other):
773 if self.isVec:
774 curMap = self.simobj._port_map.get(self.name, [])
775 self.index = len(curMap)
776 curMap.append(other)
777 else:
778 curMap = self.simobj._port_map.get(self.name)
779 if curMap and not self.isVec:
780 print "warning: overwriting port", self.simobj, self.name
781 curMap = other
782 self.simobj._port_map[self.name] = curMap
783 self.peer = other
784
785 def clone(self, memo):
786 newRef = copy.copy(self)
787 assert(isSimObject(newRef.simobj))
788 newRef.simobj = newRef.simobj(_memo=memo)
789 # Tricky: if I'm the *second* PortRef in the pair to be
790 # cloned, then my peer is still in the middle of its clone
791 # method, and thus hasn't returned to its owner's
792 # SimObject.__init__ to get installed in _port_map. As a
793 # result I have no way of finding the *new* peer object. So I
794 # mark myself as "waiting" for my peer, and I let the *first*
795 # PortRef clone call set up both peer pointers after I return.
796 newPeer = newRef.simobj._port_map.get(self.name)
797 if newPeer:
798 if self.isVec:
799 assert(self.index != -1)
800 newPeer = newPeer[self.index]
801 # other guy is all set up except for his peer pointer
802 assert(newPeer.peer == -1) # peer must be waiting for handshake
803 newPeer.peer = newRef
804 newRef.peer = newPeer
805 else:
806 # other guy is in clone; just wait for him to do the work
807 newRef.peer = -1 # mark as waiting for handshake
808 return newRef
809
810 # Call C++ to create corresponding port connection between C++ objects
811 def ccConnect(self):
812 if self.ccConnected: # already done this
813 return
814 peer = self.peer
815 cc_main.connectPorts(self.simobj.getCCObject(), self.name, self.index,
816 peer.simobj.getCCObject(), peer.name, peer.index)
817 self.ccConnected = True
818 peer.ccConnected = True
819
820# Port description object. Like a ParamDesc object, this represents a
821# logical port in the SimObject class, not a particular port on a
822# SimObject instance. The latter are represented by PortRef objects.
823class Port(object):
824 def __init__(self, desc):
825 self.desc = desc
826 self.isVec = False
827
828 # Generate a PortRef for this port on the given SimObject with the
829 # given name
830 def makeRef(self, simobj, name):
831 return PortRef(simobj, name, self.isVec)
832
833 # Connect an instance of this port (on the given SimObject with
834 # the given name) with the port described by the supplied PortRef
835 def connect(self, simobj, name, ref):
836 if not isinstance(ref, PortRef):
837 raise TypeError, \
838 "assigning non-port reference port '%s'" % name
839 myRef = self.makeRef(simobj, name)
840 myRef.setPeer(ref)
841 ref.setPeer(myRef)
842
843# VectorPort description object. Like Port, but represents a vector
844# of connections (e.g., as on a Bus).
845class VectorPort(Port):
846 def __init__(self, desc):
847 Port.__init__(self, desc)
848 self.isVec = True
849
850
851__all__ = ['Param', 'VectorParam',
852 'Enum', 'Bool', 'String', 'Float',
853 'Int', 'Unsigned', 'Int8', 'UInt8', 'Int16', 'UInt16',
854 'Int32', 'UInt32', 'Int64', 'UInt64',
855 'Counter', 'Addr', 'Tick', 'Percent',
856 'TcpPort', 'UdpPort', 'EthernetAddr',
857 'MemorySize', 'MemorySize32',
858 'Latency', 'Frequency', 'RootClock', 'Clock',
859 'NetworkBandwidth', 'MemoryBandwidth',
860 'Range', 'AddrRange', 'TickRange',
861 'MaxAddr', 'MaxTick', 'AllMemory',
862 'NextEthernetAddr', 'NULL',
863 'Port', 'VectorPort']
864
865# see comment on imports at end of __init__.py.
866from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass
867import proxy
868import objects
869import cc_main