1// Copyright (c) 2013 ARM Limited 2// All rights reserved 3// 4// The license below extends only to copyright in the software and shall 5// not be construed as granting a license to any other intellectual 6// property including but not limited to intellectual property relating 7// to a hardware implementation of the functionality of the software 8// licensed hereunder. You may use the software subject to the license --- 36 unchanged lines hidden (view full) --- 45message InstDepRecordHeader { 46 required string obj_id = 1; 47 optional uint32 ver = 2 [default = 0]; 48 required uint64 tick_freq = 3; 49 required uint32 window_size = 4; 50} 51 52// Packet to encapsulate an instruction in the o3cpu data dependency trace. |
53// The required fields include the instruction sequence number and the type 54// of the record associated with the instruction e.g. load. The request related 55// fields are optional, namely address, size and flags. The dependency related 56// information includes a repeated field for order dependencies and register 57// dependencies for loads, stores and comp records. There is a field for the 58// computational delay with respect to the dependency that completed last. A 59// weight field is used to account for committed instruction that were 60// filtered out before writing the trace and is used to estimate ROB 61// occupancy during replay. An optional field is provided for the instruction 62// PC. |
63message InstDepRecord { |
64 enum RecordType { 65 INVALID = 0; 66 LOAD = 1; 67 STORE = 2; 68 COMP = 3; 69 } |
70 required uint64 seq_num = 1; |
71 required RecordType type = 2 [default = INVALID]; 72 optional uint64 addr = 3; 73 optional uint32 size = 4; 74 optional uint32 flags = 5; 75 repeated uint64 rob_dep = 6; 76 required uint64 comp_delay = 7; 77 repeated uint64 reg_dep = 8; 78 optional uint32 weight = 9; 79 optional uint64 pc = 10; |
80} |