1// Copyright (c) 2013 ARM Limited
2// All rights reserved
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
7// to a hardware implementation of the functionality of the software
8// licensed hereunder. You may use the software subject to the license

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45message InstDepRecordHeader {
46 required string obj_id = 1;
47 optional uint32 ver = 2 [default = 0];
48 required uint64 tick_freq = 3;
49 required uint32 window_size = 4;
50}
51
52// Packet to encapsulate an instruction in the o3cpu data dependency trace.
53// The required fields include the instruction sequence number, whether it
54// is a load, and whether it is a store. The request related fields are
55// optional, namely address, size and flags. These exist only if the
56// instruction is a load or store. The dependency related information includes
57// a repeated field for order dependencies, a repeated field for register
58// dependencies and the computational delay with respect to the dependency
59// that completed last. A weight field is used to account for committed
60// instructions that were filtered out before writing the trace and is used
61// to estimate ROB occupancy during replay. An optional field is provided for
62// the instruction PC.
63message InstDepRecord {
64 required uint64 seq_num = 1;
65 required bool load = 2;
66 required bool store = 3;
67 optional uint64 addr = 4;
68 optional uint32 size = 5;
69 optional uint32 flags = 6;
70 repeated uint64 rob_dep = 7;
71 required uint64 comp_delay = 8;
72 repeated uint64 reg_dep = 9;
73 optional uint32 weight = 10;
74 optional uint64 pc = 11;
75}