xbar.cc (13808:0a44fbc3a853) xbar.cc (13892:0182a0601f66)
1/*
2 * Copyright (c) 2011-2015, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51
52#include "base/logging.hh"
53#include "base/trace.hh"
54#include "debug/AddrRanges.hh"
55#include "debug/Drain.hh"
56#include "debug/XBar.hh"
57
58BaseXBar::BaseXBar(const BaseXBarParams *p)
1/*
2 * Copyright (c) 2011-2015, 2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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51
52#include "base/logging.hh"
53#include "base/trace.hh"
54#include "debug/AddrRanges.hh"
55#include "debug/Drain.hh"
56#include "debug/XBar.hh"
57
58BaseXBar::BaseXBar(const BaseXBarParams *p)
59 : MemObject(p),
59 : ClockedObject(p),
60 frontendLatency(p->frontend_latency),
61 forwardLatency(p->forward_latency),
62 responseLatency(p->response_latency),
63 width(p->width),
64 gotAddrRanges(p->port_default_connection_count +
65 p->port_master_connection_count, false),
66 gotAllAddrRanges(false), defaultPortID(InvalidPortID),
67 useDefaultRange(p->use_default_range)

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83 // the master port index translates directly to the vector position
84 return *masterPorts[idx];
85 } else if (if_name == "default") {
86 return *masterPorts[defaultPortID];
87 } else if (if_name == "slave" && idx < slavePorts.size()) {
88 // the slave port index translates directly to the vector position
89 return *slavePorts[idx];
90 } else {
60 frontendLatency(p->frontend_latency),
61 forwardLatency(p->forward_latency),
62 responseLatency(p->response_latency),
63 width(p->width),
64 gotAddrRanges(p->port_default_connection_count +
65 p->port_master_connection_count, false),
66 gotAllAddrRanges(false), defaultPortID(InvalidPortID),
67 useDefaultRange(p->use_default_range)

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83 // the master port index translates directly to the vector position
84 return *masterPorts[idx];
85 } else if (if_name == "default") {
86 return *masterPorts[defaultPortID];
87 } else if (if_name == "slave" && idx < slavePorts.size()) {
88 // the slave port index translates directly to the vector position
89 return *slavePorts[idx];
90 } else {
91 return MemObject::getPort(if_name, idx);
91 return ClockedObject::getPort(if_name, idx);
92 }
93}
94
95void
96BaseXBar::calcPacketTiming(PacketPtr pkt, Tick header_delay)
97{
98 // the crossbar will be called at a time that is not necessarily
99 // coinciding with its own clock, so start by determining how long

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93}
94
95void
96BaseXBar::calcPacketTiming(PacketPtr pkt, Tick header_delay)
97{
98 // the crossbar will be called at a time that is not necessarily
99 // coinciding with its own clock, so start by determining how long

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