1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Andreas Hansson
42 */
43
44#ifndef __MEM_TPORT_HH__
45#define __MEM_TPORT_HH__
46
47/**
48 * @file
49 *
50 * Declaration of SimpleTimingPort.
51 */
52
53#include "mem/qport.hh"
54
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 * Andreas Hansson
42 */
43
44#ifndef __MEM_TPORT_HH__
45#define __MEM_TPORT_HH__
46
47/**
48 * @file
49 *
50 * Declaration of SimpleTimingPort.
51 */
52
53#include "mem/qport.hh"
54
|
55/**
56 * The simple timing port uses a queued port to implement
57 * recvFunctional and recvTimingReq through recvAtomic. It is always a
58 * slave port.
59 */
60class SimpleTimingPort : public QueuedSlavePort
61{
62
63 private:
64
65 /**
66 * The packet queue used to store outgoing responses. Note that
67 * the queue is made private and that we avoid overloading the
68 * name used in the QueuedSlavePort. Access is provided through
69 * the queue reference in the base class.
70 */
71 RespPacketQueue queueImpl;
72
73 protected:
74
75 /** Implemented using recvAtomic(). */
76 void recvFunctional(PacketPtr pkt);
77
78 /** Implemented using recvAtomic(). */
79 bool recvTimingReq(PacketPtr pkt);
80
81 virtual Tick recvAtomic(PacketPtr pkt) = 0;
82
83 /**
84 * Upstream caches need this packet until true is returned, so
85 * hold it for deletion until a subsequent call
86 */
87 std::unique_ptr<Packet> pendingDelete;
88
89 public:
90
91 /**
92 * Create a new SimpleTimingPort that relies on a packet queue to
93 * hold responses, and implements recvTimingReq and recvFunctional
94 * through calls to recvAtomic. Once a request arrives, it is
95 * passed to recvAtomic, and in the case of a timing access any
96 * response is scheduled to be sent after the delay of the atomic
97 * operation.
98 *
99 * @param name port name
100 * @param owner structural owner
101 */
| 57/**
58 * The simple timing port uses a queued port to implement
59 * recvFunctional and recvTimingReq through recvAtomic. It is always a
60 * slave port.
61 */
62class SimpleTimingPort : public QueuedSlavePort
63{
64
65 private:
66
67 /**
68 * The packet queue used to store outgoing responses. Note that
69 * the queue is made private and that we avoid overloading the
70 * name used in the QueuedSlavePort. Access is provided through
71 * the queue reference in the base class.
72 */
73 RespPacketQueue queueImpl;
74
75 protected:
76
77 /** Implemented using recvAtomic(). */
78 void recvFunctional(PacketPtr pkt);
79
80 /** Implemented using recvAtomic(). */
81 bool recvTimingReq(PacketPtr pkt);
82
83 virtual Tick recvAtomic(PacketPtr pkt) = 0;
84
85 /**
86 * Upstream caches need this packet until true is returned, so
87 * hold it for deletion until a subsequent call
88 */
89 std::unique_ptr<Packet> pendingDelete;
90
91 public:
92
93 /**
94 * Create a new SimpleTimingPort that relies on a packet queue to
95 * hold responses, and implements recvTimingReq and recvFunctional
96 * through calls to recvAtomic. Once a request arrives, it is
97 * passed to recvAtomic, and in the case of a timing access any
98 * response is scheduled to be sent after the delay of the atomic
99 * operation.
100 *
101 * @param name port name
102 * @param owner structural owner
103 */
|