tport.hh (11190:0964165d1857) | tport.hh (13892:0182a0601f66) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 38 unchanged lines hidden (view full) --- 47/** 48 * @file 49 * 50 * Declaration of SimpleTimingPort. 51 */ 52 53#include "mem/qport.hh" 54 | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 38 unchanged lines hidden (view full) --- 47/** 48 * @file 49 * 50 * Declaration of SimpleTimingPort. 51 */ 52 53#include "mem/qport.hh" 54 |
55class SimObject; 56 |
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55/** 56 * The simple timing port uses a queued port to implement 57 * recvFunctional and recvTimingReq through recvAtomic. It is always a 58 * slave port. 59 */ 60class SimpleTimingPort : public QueuedSlavePort 61{ 62 --- 31 unchanged lines hidden (view full) --- 94 * through calls to recvAtomic. Once a request arrives, it is 95 * passed to recvAtomic, and in the case of a timing access any 96 * response is scheduled to be sent after the delay of the atomic 97 * operation. 98 * 99 * @param name port name 100 * @param owner structural owner 101 */ | 57/** 58 * The simple timing port uses a queued port to implement 59 * recvFunctional and recvTimingReq through recvAtomic. It is always a 60 * slave port. 61 */ 62class SimpleTimingPort : public QueuedSlavePort 63{ 64 --- 31 unchanged lines hidden (view full) --- 96 * through calls to recvAtomic. Once a request arrives, it is 97 * passed to recvAtomic, and in the case of a timing access any 98 * response is scheduled to be sent after the delay of the atomic 99 * operation. 100 * 101 * @param name port name 102 * @param owner structural owner 103 */ |
102 SimpleTimingPort(const std::string& name, MemObject* owner); | 104 SimpleTimingPort(const std::string& name, SimObject* owner); |
103 104 virtual ~SimpleTimingPort() { } 105 106}; 107 108#endif // __MEM_TPORT_HH__ | 105 106 virtual ~SimpleTimingPort() { } 107 108}; 109 110#endif // __MEM_TPORT_HH__ |