1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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48 MemObject* _owner) :
49 QueuedSlavePort(_name, _owner, queue), queue(*_owner, *this)
50{
51}
52
53void
54SimpleTimingPort::recvFunctional(PacketPtr pkt)
55{
56 assert(pkt->isRequest());
56 if (!queue.checkFunctional(pkt)) {
57 // do an atomic access and throw away the returned latency
58 recvAtomic(pkt);
59 }
60}
61
62bool
64SimpleTimingPort::recvTiming(PacketPtr pkt)
63SimpleTimingPort::recvTimingReq(PacketPtr pkt)
64{
66 // the port is a slave and should hence only get timing requests
67 assert(pkt->isRequest());
68
65 if (pkt->memInhibitAsserted()) {
66 // snooper will supply based on copy of packet
67 // still target's responsibility to delete packet
68 delete pkt;
69 return true;
70 }
71
72 bool needsResponse = pkt->needsResponse();

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