1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 28 unchanged lines hidden (view full) --- 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Andreas Hansson 42 */ 43 44#include "mem/tport.hh" |
45#include "sim/sim_object.hh" |
46 |
47SimpleTimingPort::SimpleTimingPort(const std::string& _name, |
48 SimObject* _owner) : |
49 QueuedSlavePort(_name, _owner, queueImpl), queueImpl(*_owner, *this) 50{ 51} 52 53void 54SimpleTimingPort::recvFunctional(PacketPtr pkt) 55{ 56 if (!respQueue.trySatisfyFunctional(pkt)) { --- 30 unchanged lines hidden --- |