StateMachine.py (9496:28d88a0fda74) StateMachine.py (9499:b03b556a8fbb)
1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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27
28from m5.util import orderdict
29
30from slicc.symbols.Symbol import Symbol
31from slicc.symbols.Var import Var
32import slicc.generate.html as html
33import re
34
1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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27
28from m5.util import orderdict
29
30from slicc.symbols.Symbol import Symbol
31from slicc.symbols.Var import Var
32import slicc.generate.html as html
33import re
34
35python_class_map = {"int": "Int",
35python_class_map = {
36 "int": "Int",
36 "uint32_t" : "UInt32",
37 "std::string": "String",
38 "bool": "Bool",
39 "CacheMemory": "RubyCache",
40 "WireBuffer": "RubyWireBuffer",
41 "Sequencer": "RubySequencer",
42 "DirectoryMemory": "RubyDirectoryMemory",
43 "MemoryControl": "MemoryControl",
44 "DMASequencer": "DMASequencer",
37 "uint32_t" : "UInt32",
38 "std::string": "String",
39 "bool": "Bool",
40 "CacheMemory": "RubyCache",
41 "WireBuffer": "RubyWireBuffer",
42 "Sequencer": "RubySequencer",
43 "DirectoryMemory": "RubyDirectoryMemory",
44 "MemoryControl": "MemoryControl",
45 "DMASequencer": "DMASequencer",
45 "Prefetcher":"Prefetcher"
46 }
46 "Prefetcher":"Prefetcher",
47 "Cycles":"Cycles",
48 }
47
48class StateMachine(Symbol):
49 def __init__(self, symtab, ident, location, pairs, config_parameters):
50 super(StateMachine, self).__init__(symtab, ident, location, pairs)
51 self.table = None
52 self.config_parameters = config_parameters
53 self.prefetchers = []
54

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624 # set description (may be overriden later by port def)
625 code('''
626$vid->setDescription("[Version " + to_string(m_version) + ", ${ident}, name=${{var.c_ident}}]");
627
628''')
629
630 if vtype.isBuffer:
631 if "recycle_latency" in var:
49
50class StateMachine(Symbol):
51 def __init__(self, symtab, ident, location, pairs, config_parameters):
52 super(StateMachine, self).__init__(symtab, ident, location, pairs)
53 self.table = None
54 self.config_parameters = config_parameters
55 self.prefetchers = []
56

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626 # set description (may be overriden later by port def)
627 code('''
628$vid->setDescription("[Version " + to_string(m_version) + ", ${ident}, name=${{var.c_ident}}]");
629
630''')
631
632 if vtype.isBuffer:
633 if "recycle_latency" in var:
632 code('$vid->setRecycleLatency(${{var["recycle_latency"]}});')
634 code('$vid->setRecycleLatency( ' \
635 'Cycles(${{var["recycle_latency"]}}));')
633 else:
634 code('$vid->setRecycleLatency(m_recycle_latency);')
635
636 # Set the prefetchers
637 code()
638 for prefetcher in self.prefetchers:
639 code('${{prefetcher.code}}.setController(this);')
640

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1050 while (true) {
1051 // Some cases will put us into an infinite loop without this limit
1052 assert(counter <= m_transitions_per_cycle);
1053 if (counter == m_transitions_per_cycle) {
1054 // Count how often we are fully utilized
1055 m_fully_busy_cycles++;
1056
1057 // Wakeup in another cycle and try again
636 else:
637 code('$vid->setRecycleLatency(m_recycle_latency);')
638
639 # Set the prefetchers
640 code()
641 for prefetcher in self.prefetchers:
642 code('${{prefetcher.code}}.setController(this);')
643

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1053 while (true) {
1054 // Some cases will put us into an infinite loop without this limit
1055 assert(counter <= m_transitions_per_cycle);
1056 if (counter == m_transitions_per_cycle) {
1057 // Count how often we are fully utilized
1058 m_fully_busy_cycles++;
1059
1060 // Wakeup in another cycle and try again
1058 scheduleEvent(1);
1061 scheduleEvent(Cycles(1));
1059 break;
1060 }
1061''')
1062
1063 code.indent()
1064 code.indent()
1065
1066 # InPorts

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1063 }
1064''')
1065
1066 code.indent()
1067 code.indent()
1068
1069 # InPorts

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