StateMachine.py (8187:99428f716e7b) StateMachine.py (8189:d5ad24eb015f)
1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
28from m5.util import orderdict
29
30from slicc.symbols.Symbol import Symbol
31from slicc.symbols.Var import Var
32import slicc.generate.html as html
1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

--- 16 unchanged lines hidden (view full) ---

25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
28from m5.util import orderdict
29
30from slicc.symbols.Symbol import Symbol
31from slicc.symbols.Var import Var
32import slicc.generate.html as html
33import re
33
34python_class_map = {"int": "Int",
35 "std::string": "String",
36 "bool": "Bool",
37 "CacheMemory": "RubyCache",
38 "Sequencer": "RubySequencer",
39 "DirectoryMemory": "RubyDirectoryMemory",
40 "MemoryControl": "RubyMemoryControl",

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468 code.indent()
469
470 #
471 # After initializing the universal machine parameters, initialize the
472 # this machines config parameters. Also detemine if these configuration
473 # params include a sequencer. This information will be used later for
474 # contecting the sequencer back to the L1 cache controller.
475 #
34
35python_class_map = {"int": "Int",
36 "std::string": "String",
37 "bool": "Bool",
38 "CacheMemory": "RubyCache",
39 "Sequencer": "RubySequencer",
40 "DirectoryMemory": "RubyDirectoryMemory",
41 "MemoryControl": "RubyMemoryControl",

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469 code.indent()
470
471 #
472 # After initializing the universal machine parameters, initialize the
473 # this machines config parameters. Also detemine if these configuration
474 # params include a sequencer. This information will be used later for
475 # contecting the sequencer back to the L1 cache controller.
476 #
476 contains_sequencer = False
477 contains_dma_sequencer = False
478 sequencers = []
477 for param in self.config_parameters:
479 for param in self.config_parameters:
478 if param.name == "sequencer" or param.name == "dma_sequencer":
479 contains_sequencer = True
480 if param.name == "dma_sequencer":
481 contains_dma_sequencer = True
482 elif re.compile("sequencer").search(param.name):
483 sequencers.append(param.name)
480 if param.pointer:
481 code('m_${{param.name}}_ptr = p->${{param.name}};')
482 else:
483 code('m_${{param.name}} = p->${{param.name}};')
484
485 #
486 # For the l1 cache controller, add the special atomic support which
487 # includes passing the sequencer a pointer to the controller.
488 #
489 if self.ident == "L1Cache":
484 if param.pointer:
485 code('m_${{param.name}}_ptr = p->${{param.name}};')
486 else:
487 code('m_${{param.name}} = p->${{param.name}};')
488
489 #
490 # For the l1 cache controller, add the special atomic support which
491 # includes passing the sequencer a pointer to the controller.
492 #
493 if self.ident == "L1Cache":
490 if not contains_sequencer:
494 if not sequencers:
491 self.error("The L1Cache controller must include the sequencer " \
492 "configuration parameter")
493
495 self.error("The L1Cache controller must include the sequencer " \
496 "configuration parameter")
497
494 code('''
495m_sequencer_ptr->setController(this);
496''')
498 for seq in sequencers:
499 code('''
500m_${{seq}}_ptr->setController(this);
501 ''')
497 #
498 # For the DMA controller, pass the sequencer a pointer to the
499 # controller.
500 #
501 if self.ident == "DMA":
502 #
503 # For the DMA controller, pass the sequencer a pointer to the
504 # controller.
505 #
506 if self.ident == "DMA":
502 if not contains_sequencer:
507 if not contains_dma_sequencer:
503 self.error("The DMA controller must include the sequencer " \
504 "configuration parameter")
505
506 code('''
507m_dma_sequencer_ptr->setController(this);
508''')
509
510 code('m_num_controllers++;')

--- 1129 unchanged lines hidden --- 		508 self.error("The DMA controller must include the sequencer " \
509 "configuration parameter")
510
511 code('''
512m_dma_sequencer_ptr->setController(this);
513''')
514
515 code('m_num_controllers++;')

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