StateMachine.py (7025:9adf5b0ccc79) StateMachine.py (7055:4e24742201d7)
1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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27
28from m5.util import orderdict
29
30from slicc.symbols.Symbol import Symbol
31from slicc.symbols.Var import Var
32import slicc.generate.html as html
33
34python_class_map = {"int": "Int",
1# Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
2# Copyright (c) 2009 The Hewlett-Packard Development Company
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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27
28from m5.util import orderdict
29
30from slicc.symbols.Symbol import Symbol
31from slicc.symbols.Var import Var
32import slicc.generate.html as html
33
34python_class_map = {"int": "Int",
35 "string": "String",
35 "std::string": "String",
36 "bool": "Bool",
37 "CacheMemory": "RubyCache",
38 "Sequencer": "RubySequencer",
39 "DirectoryMemory": "RubyDirectoryMemory",
40 "MemoryControl": "RubyMemoryControl",
41 "DMASequencer": "DMASequencer"
42 }
43

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266 ${ident}_State state,
267 ${ident}_State& next_state,
268 const Address& addr);
269
270std::string m_name;
271int m_transitions_per_cycle;
272int m_buffer_size;
273int m_recycle_latency;
36 "bool": "Bool",
37 "CacheMemory": "RubyCache",
38 "Sequencer": "RubySequencer",
39 "DirectoryMemory": "RubyDirectoryMemory",
40 "MemoryControl": "RubyMemoryControl",
41 "DMASequencer": "DMASequencer"
42 }
43

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266 ${ident}_State state,
267 ${ident}_State& next_state,
268 const Address& addr);
269
270std::string m_name;
271int m_transitions_per_cycle;
272int m_buffer_size;
273int m_recycle_latency;
274map m_cfg;
274std::map<std::string, std::string> m_cfg;
275NodeID m_version;
276Network* m_net_ptr;
277MachineID m_machineID;
278bool m_is_blocking;
275NodeID m_version;
276Network* m_net_ptr;
277MachineID m_machineID;
278bool m_is_blocking;
279map< Address, MessageBuffer* > m_block_map;
279std::map<Address, MessageBuffer*> m_block_map;
280${ident}_Profiler s_profiler;
281static int m_num_controllers;
282
283// Internal functions
284''')
285
286 for func in self.functions:
287 proto = func.prototype

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709#include "mem/ruby/common/Global.hh"
710#include "mem/ruby/slicc_interface/RubySlicc_includes.hh"
711#include "mem/protocol/${ident}_Controller.hh"
712#include "mem/protocol/${ident}_State.hh"
713#include "mem/protocol/${ident}_Event.hh"
714#include "mem/protocol/Types.hh"
715#include "mem/ruby/system/System.hh"
716
280${ident}_Profiler s_profiler;
281static int m_num_controllers;
282
283// Internal functions
284''')
285
286 for func in self.functions:
287 proto = func.prototype

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709#include "mem/ruby/common/Global.hh"
710#include "mem/ruby/slicc_interface/RubySlicc_includes.hh"
711#include "mem/protocol/${ident}_Controller.hh"
712#include "mem/protocol/${ident}_State.hh"
713#include "mem/protocol/${ident}_Event.hh"
714#include "mem/protocol/Types.hh"
715#include "mem/ruby/system/System.hh"
716
717using namespace std;
718
717void
718${ident}_Controller::wakeup()
719{
720 // DEBUG_EXPR(GENERATED_COMP, MedPrio, *this);
721 // DEBUG_EXPR(GENERATED_COMP, MedPrio, g_eventQueue_ptr->getTime());
722
723 int counter = 0;
724 while (true) {

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720${ident}_Controller::wakeup()
721{
722 // DEBUG_EXPR(GENERATED_COMP, MedPrio, *this);
723 // DEBUG_EXPR(GENERATED_COMP, MedPrio, g_eventQueue_ptr->getTime());
724
725 int counter = 0;
726 while (true) {

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